
FEB_4052 17.07.24 09:55:13
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09:55:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 09:55:13:ST3_Shared:INFO: FEB-Microcable 09:55:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 09:55:13:febtest:INFO: Testing FEB with SN 4052 09:55:15:smx_tester:INFO: Scanning setup 09:55:15:elinks:INFO: Disabling clock on downlink 0 09:55:15:elinks:INFO: Disabling clock on downlink 1 09:55:15:elinks:INFO: Disabling clock on downlink 2 09:55:15:elinks:INFO: Disabling clock on downlink 3 09:55:15:elinks:INFO: Disabling clock on downlink 4 09:55:15:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:55:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 09:55:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:55:15:elinks:INFO: Disabling clock on downlink 0 09:55:15:elinks:INFO: Disabling clock on downlink 1 09:55:15:elinks:INFO: Disabling clock on downlink 2 09:55:15:elinks:INFO: Disabling clock on downlink 3 09:55:15:elinks:INFO: Disabling clock on downlink 4 09:55:15:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:55:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 09:55:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:55:15:elinks:INFO: Disabling clock on downlink 0 09:55:15:elinks:INFO: Disabling clock on downlink 1 09:55:15:elinks:INFO: Disabling clock on downlink 2 09:55:15:elinks:INFO: Disabling clock on downlink 3 09:55:15:elinks:INFO: Disabling clock on downlink 4 09:55:15:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:55:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30 09:55:15:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31 09:55:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:55:15:elinks:INFO: Disabling clock on downlink 0 09:55:15:elinks:INFO: Disabling clock on downlink 1 09:55:15:elinks:INFO: Disabling clock on downlink 2 09:55:15:elinks:INFO: Disabling clock on downlink 3 09:55:15:elinks:INFO: Disabling clock on downlink 4 09:55:15:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:55:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 09:55:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:55:15:elinks:INFO: Disabling clock on downlink 0 09:55:15:elinks:INFO: Disabling clock on downlink 1 09:55:15:elinks:INFO: Disabling clock on downlink 2 09:55:15:elinks:INFO: Disabling clock on downlink 3 09:55:15:elinks:INFO: Disabling clock on downlink 4 09:55:16:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:55:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 09:55:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:55:16:setup_element:INFO: Scanning clock phase 09:55:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:55:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:55:16:setup_element:INFO: Clock phase scan results for group 0, downlink 2 09:55:16:setup_element:INFO: Eye window for uplink 24: ________________________________________________________________XXXXXXX_________ Clock Delay: 27 09:55:16:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________XXXXXXX_________ Clock Delay: 27 09:55:16:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:55:16:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:55:16:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________XXXXXX___________ Clock Delay: 25 09:55:16:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________XXXXXX___________ Clock Delay: 25 09:55:16:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________XXXXXX___________ Clock Delay: 25 09:55:16:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________XXXXXX___________ Clock Delay: 25 09:55:16:setup_element:INFO: Setting the clock phase to 26 for group 0, downlink 2 09:55:16:setup_element:INFO: Scanning data phases 09:55:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:55:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:55:21:setup_element:INFO: Data phase scan results for group 0, downlink 2 09:55:21:setup_element:INFO: Eye window for uplink 24: _______XXXXXXX__________________________ Data delay found: 30 09:55:21:setup_element:INFO: Eye window for uplink 25: ___________XXXXXX_______________________ Data delay found: 33 09:55:21:setup_element:INFO: Eye window for uplink 26: ____XXXXXXXX____________________________ Data delay found: 27 09:55:21:setup_element:INFO: Eye window for uplink 27: ________XXXXXXXXX_______________________ Data delay found: 32 09:55:21:setup_element:INFO: Eye window for uplink 28: ___________XXXXXXXX_____________________ Data delay found: 34 09:55:21:setup_element:INFO: Eye window for uplink 29: _______________XXXXXXX__________________ Data delay found: 38 09:55:21:setup_element:INFO: Eye window for uplink 30: _____________XXXXXXXX___________________ Data delay found: 36 09:55:21:setup_element:INFO: Eye window for uplink 31: ______________XXXXXXXX__________________ Data delay found: 37 09:55:21:setup_element:INFO: Setting the data phase to 30 for uplink 24 09:55:21:setup_element:INFO: Setting the data phase to 33 for uplink 25 09:55:21:setup_element:INFO: Setting the data phase to 27 for uplink 26 09:55:21:setup_element:INFO: Setting the data phase to 32 for uplink 27 09:55:21:setup_element:INFO: Setting the data phase to 34 for uplink 28 09:55:21:setup_element:INFO: Setting the data phase to 38 for uplink 29 09:55:21:setup_element:INFO: Setting the data phase to 36 for uplink 30 09:55:21:setup_element:INFO: Setting the data phase to 37 for uplink 31 09:55:21:setup_element:INFO: Beginning SMX ASICs map scan 09:55:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:55:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:55:21:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 09:55:21:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 09:55:21:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31] 09:55:21:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30 09:55:21:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31 09:55:22:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28 09:55:22:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29 09:55:22:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26 09:55:22:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27 09:55:22:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24 09:55:22:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25 09:55:24:setup_element:INFO: Performing Elink synchronization 09:55:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:55:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:55:24:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 09:55:24:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 09:55:24:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2 09:55:24:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31] |_________________________________________________________________________| _addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_ 1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)] 3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)] 5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)] 7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)] |_________________________________________________________________________| 09:55:24:febtest:INFO: Init all SMX (CSA): 30 09:55:34:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 09:55:34:febtest:INFO: 30-01 | XA-000-08-003-000-002-077-02 | 34.6 | 1177.4 09:55:34:febtest:INFO: 28-03 | XA-000-08-003-000-002-072-02 | 40.9 | 1153.7 09:55:34:febtest:INFO: 26-05 | XA-000-08-003-000-002-080-05 | 15.6 | 1242.0 09:55:35:febtest:INFO: 24-07 | XA-000-08-003-000-002-076-02 | 34.6 | 1165.6 09:55:36:febtest:INFO: Set all CSA to ZERO FEB type: B FEB_A: 0 FEB_B: 1 09:55:38:ST3_smx:INFO: chip: 30-1 34.556970 C 1183.292940 mV 09:55:38:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:38:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:38:ST3_smx:INFO: Electrons 09:55:38:ST3_smx:INFO: # loops 0 09:55:40:ST3_smx:INFO: # loops 1 09:55:42:ST3_smx:INFO: # loops 2 09:55:44:ST3_smx:INFO: Total # of broken channels: 0 09:55:44:ST3_smx:INFO: List of broken channels: [] 09:55:44:ST3_smx:INFO: Total # of broken channels: 0 09:55:44:ST3_smx:INFO: List of broken channels: [] 09:55:45:ST3_smx:INFO: chip: 28-3 40.898880 C 1165.571835 mV 09:55:45:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:45:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:45:ST3_smx:INFO: Electrons 09:55:45:ST3_smx:INFO: # loops 0 09:55:47:ST3_smx:INFO: # loops 1 09:55:49:ST3_smx:INFO: # loops 2 09:55:52:ST3_smx:INFO: Total # of broken channels: 0 09:55:52:ST3_smx:INFO: List of broken channels: [] 09:55:52:ST3_smx:INFO: Total # of broken channels: 0 09:55:52:ST3_smx:INFO: List of broken channels: [] 09:55:53:ST3_smx:INFO: chip: 26-5 15.590880 C 1247.887635 mV 09:55:53:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:53:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:55:53:ST3_smx:INFO: Electrons 09:55:53:ST3_smx:INFO: # loops 0 09:55:55:ST3_smx:INFO: # loops 1 09:55:58:ST3_smx:INFO: # loops 2 09:56:00:ST3_smx:INFO: Total # of broken channels: 0 09:56:00:ST3_smx:INFO: List of broken channels: [] 09:56:00:ST3_smx:INFO: Total # of broken channels: 0 09:56:00:ST3_smx:INFO: List of broken channels: [] 09:56:02:ST3_smx:INFO: chip: 24-7 37.726682 C 1171.483840 mV 09:56:02:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:56:02:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:56:02:ST3_smx:INFO: Electrons 09:56:02:ST3_smx:INFO: # loops 0 09:56:04:ST3_smx:INFO: # loops 1 09:56:05:ST3_smx:INFO: # loops 2 09:56:08:ST3_smx:INFO: Total # of broken channels: 0 09:56:08:ST3_smx:INFO: List of broken channels: [] 09:56:08:ST3_smx:INFO: Total # of broken channels: 0 09:56:08:ST3_smx:INFO: List of broken channels: [] 09:56:08:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 09:56:08:febtest:INFO: 30-01 | XA-000-08-003-000-002-077-02 | 34.6 | 1212.7 09:56:08:febtest:INFO: 28-03 | XA-000-08-003-000-002-072-02 | 40.9 | 1183.3 09:56:09:febtest:INFO: 26-05 | XA-000-08-003-000-002-080-05 | 18.7 | 1271.2 09:56:09:febtest:INFO: 24-07 | XA-000-08-003-000-002-076-02 | 37.7 | 1206.9 ############################################################ # S U M M A R Y # ############################################################ {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Microcable TEST_DATE : 24_07_17-09_55_13 OPERATOR : Benjamin; SITE : KIT | SETUP : KIT_TEST_SETUP_1 ------------------------------------------------------------ | FEB_SN : 4052| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B ------------------------------------------------------------ ------------------------------------------------------------ VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.451', '0.7081', '1.850', '1.0780'] VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9910', '1.850', '1.2220'] VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9707', '1.850', '0.2614']