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FEB_4052 17.07.24 12:53:30
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12:53:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:53:30:ST3_Shared:INFO: FEB-Microcable
12:53:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:53:30:febtest:INFO: Testing FEB with SN 4052
12:53:31:smx_tester:INFO: Scanning setup
12:53:31:elinks:INFO: Disabling clock on downlink 0
12:53:31:elinks:INFO: Disabling clock on downlink 1
12:53:31:elinks:INFO: Disabling clock on downlink 2
12:53:31:elinks:INFO: Disabling clock on downlink 3
12:53:31:elinks:INFO: Disabling clock on downlink 4
12:53:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:53:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:53:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:53:32:elinks:INFO: Disabling clock on downlink 0
12:53:32:elinks:INFO: Disabling clock on downlink 1
12:53:32:elinks:INFO: Disabling clock on downlink 2
12:53:32:elinks:INFO: Disabling clock on downlink 3
12:53:32:elinks:INFO: Disabling clock on downlink 4
12:53:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:53:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:53:32:elinks:INFO: Disabling clock on downlink 0
12:53:32:elinks:INFO: Disabling clock on downlink 1
12:53:32:elinks:INFO: Disabling clock on downlink 2
12:53:32:elinks:INFO: Disabling clock on downlink 3
12:53:32:elinks:INFO: Disabling clock on downlink 4
12:53:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
12:53:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
12:53:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:53:32:elinks:INFO: Disabling clock on downlink 0
12:53:32:elinks:INFO: Disabling clock on downlink 1
12:53:32:elinks:INFO: Disabling clock on downlink 2
12:53:32:elinks:INFO: Disabling clock on downlink 3
12:53:32:elinks:INFO: Disabling clock on downlink 4
12:53:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:53:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:53:32:elinks:INFO: Disabling clock on downlink 0
12:53:32:elinks:INFO: Disabling clock on downlink 1
12:53:32:elinks:INFO: Disabling clock on downlink 2
12:53:32:elinks:INFO: Disabling clock on downlink 3
12:53:32:elinks:INFO: Disabling clock on downlink 4
12:53:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:53:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:53:32:setup_element:INFO: Scanning clock phase
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:53:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:53:32:setup_element:INFO: Clock phase scan results for group 0, downlink 2
12:53:32:setup_element:INFO: Eye window for uplink 16: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 17: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 18: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 19: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________XXXXXXX_________
Clock Delay: 27
12:53:32:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________XXXXXXX_________
Clock Delay: 27
12:53:32:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
12:53:32:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
12:53:32:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________XXXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 26: _________________________________________________________________XXXXXX_________
Clock Delay: 27
12:53:32:setup_element:INFO: Eye window for uplink 27: _________________________________________________________________XXXXXX_________
Clock Delay: 27
12:53:32:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
12:53:32:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
12:53:32:setup_element:INFO: Eye window for uplink 30: __________________________________________________________________XXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Eye window for uplink 31: __________________________________________________________________XXXXXX________
Clock Delay: 28
12:53:32:setup_element:INFO: Setting the clock phase to 27 for group 0, downlink 2
12:53:32:setup_element:INFO: Scanning data phases
12:53:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:53:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:53:38:setup_element:INFO: Data phase scan results for group 0, downlink 2
12:53:38:setup_element:INFO: Eye window for uplink 16: XXXXX_______________________________XXXX
Data delay found: 20
12:53:38:setup_element:INFO: Eye window for uplink 17: XX________________________________XXXXXX
Data delay found: 17
12:53:38:setup_element:INFO: Eye window for uplink 18: XXXXX_______________________________XXXX
Data delay found: 20
12:53:38:setup_element:INFO: Eye window for uplink 19: XX_______________________________XXXXXXX
Data delay found: 17
12:53:38:setup_element:INFO: Eye window for uplink 20: __________________________________XXXX__
Data delay found: 15
12:53:38:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXX__
Data delay found: 15
12:53:38:setup_element:INFO: Eye window for uplink 22: XXX_________________________________XXXX
Data delay found: 19
12:53:38:setup_element:INFO: Eye window for uplink 23: XXXXX___________________________XXXXXXXX
Data delay found: 18
12:53:38:setup_element:INFO: Eye window for uplink 24: _____XXXXXXXXX__________________________
Data delay found: 29
12:53:38:setup_element:INFO: Eye window for uplink 25: __________XXXXXXX_______________________
Data delay found: 33
12:53:38:setup_element:INFO: Eye window for uplink 26: _____XXXXXXX____________________________
Data delay found: 28
12:53:38:setup_element:INFO: Eye window for uplink 27: _________XXXXXXXX_______________________
Data delay found: 32
12:53:38:setup_element:INFO: Eye window for uplink 28: ______________XXXXX_____________________
Data delay found: 36
12:53:38:setup_element:INFO: Eye window for uplink 29: _______________XXXXXXXX_________________
Data delay found: 38
12:53:38:setup_element:INFO: Eye window for uplink 30: _______________XXXXXXX__________________
Data delay found: 38
12:53:38:setup_element:INFO: Eye window for uplink 31: ________________XXXXXXX_________________
Data delay found: 39
12:53:38:setup_element:INFO: Setting the data phase to 20 for uplink 16
12:53:38:setup_element:INFO: Setting the data phase to 17 for uplink 17
12:53:38:setup_element:INFO: Setting the data phase to 20 for uplink 18
12:53:38:setup_element:INFO: Setting the data phase to 17 for uplink 19
12:53:38:setup_element:INFO: Setting the data phase to 15 for uplink 20
12:53:38:setup_element:INFO: Setting the data phase to 15 for uplink 21
12:53:38:setup_element:INFO: Setting the data phase to 19 for uplink 22
12:53:38:setup_element:INFO: Setting the data phase to 18 for uplink 23
12:53:38:setup_element:INFO: Setting the data phase to 29 for uplink 24
12:53:38:setup_element:INFO: Setting the data phase to 33 for uplink 25
12:53:38:setup_element:INFO: Setting the data phase to 28 for uplink 26
12:53:38:setup_element:INFO: Setting the data phase to 32 for uplink 27
12:53:38:setup_element:INFO: Setting the data phase to 36 for uplink 28
12:53:38:setup_element:INFO: Setting the data phase to 38 for uplink 29
12:53:38:setup_element:INFO: Setting the data phase to 38 for uplink 30
12:53:38:setup_element:INFO: Setting the data phase to 39 for uplink 31
12:53:38:setup_element:INFO: Beginning SMX ASICs map scan
12:53:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:53:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:53:38:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:53:38:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:53:38:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:53:38:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
12:53:38:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
12:53:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:53:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:53:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
12:53:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
12:53:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:53:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:53:39:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
12:53:39:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
12:53:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:53:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:53:39:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
12:53:39:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
12:53:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:53:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:53:40:setup_element:INFO: Performing Elink synchronization
12:53:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:53:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:53:40:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:53:40:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:53:40:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
12:53:40:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
12:53:41:febtest:INFO: Init all SMX (CSA): 30
12:53:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:53:59:febtest:INFO: 23-00 | XA-000-08-003-000-002-071-02 | 31.4 | 1183.3
12:54:00:febtest:INFO: 30-01 | XA-000-08-003-000-002-077-02 | 34.6 | 1177.4
12:54:00:febtest:INFO: 21-02 | XA-000-08-003-000-002-079-02 | 28.2 | 1189.2
12:54:00:febtest:INFO: 28-03 | XA-000-08-003-000-002-072-02 | 37.7 | 1159.7
12:54:00:febtest:INFO: 19-04 | XA-000-08-003-000-002-074-02 | 37.7 | 1159.7
12:54:00:febtest:INFO: 26-05 | XA-000-08-003-000-002-080-05 | 12.4 | 1253.7
12:54:01:febtest:INFO: 17-06 | XA-000-08-003-000-002-070-02 | 25.1 | 1212.7
12:54:01:febtest:INFO: 24-07 | XA-000-08-003-000-002-076-02 | 34.6 | 1165.6
12:54:02:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
12:54:04:ST3_smx:INFO: chip: 23-0 31.389742 C 1189.190035 mV
12:54:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:04:ST3_smx:INFO: Electrons
12:54:04:ST3_smx:INFO: # loops 0
12:54:06:ST3_smx:INFO: # loops 1
12:54:08:ST3_smx:INFO: # loops 2
12:54:10:ST3_smx:INFO: Total # of broken channels: 0
12:54:10:ST3_smx:INFO: List of broken channels: []
12:54:10:ST3_smx:INFO: Total # of broken channels: 0
12:54:10:ST3_smx:INFO: List of broken channels: []
12:54:12:ST3_smx:INFO: chip: 30-1 34.556970 C 1189.190035 mV
12:54:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:12:ST3_smx:INFO: Electrons
12:54:12:ST3_smx:INFO: # loops 0
12:54:14:ST3_smx:INFO: # loops 1
12:54:17:ST3_smx:INFO: # loops 2
12:54:19:ST3_smx:INFO: Total # of broken channels: 0
12:54:19:ST3_smx:INFO: List of broken channels: []
12:54:19:ST3_smx:INFO: Total # of broken channels: 0
12:54:19:ST3_smx:INFO: List of broken channels: []
12:54:20:ST3_smx:INFO: chip: 21-2 28.225000 C 1200.969315 mV
12:54:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:20:ST3_smx:INFO: Electrons
12:54:20:ST3_smx:INFO: # loops 0
12:54:22:ST3_smx:INFO: # loops 1
12:54:24:ST3_smx:INFO: # loops 2
12:54:26:ST3_smx:INFO: Total # of broken channels: 0
12:54:26:ST3_smx:INFO: List of broken channels: []
12:54:26:ST3_smx:INFO: Total # of broken channels: 0
12:54:26:ST3_smx:INFO: List of broken channels: []
12:54:28:ST3_smx:INFO: chip: 28-3 40.898880 C 1171.483840 mV
12:54:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:28:ST3_smx:INFO: Electrons
12:54:28:ST3_smx:INFO: # loops 0
12:54:30:ST3_smx:INFO: # loops 1
12:54:32:ST3_smx:INFO: # loops 2
12:54:34:ST3_smx:INFO: Total # of broken channels: 0
12:54:34:ST3_smx:INFO: List of broken channels: []
12:54:34:ST3_smx:INFO: Total # of broken channels: 0
12:54:34:ST3_smx:INFO: List of broken channels: []
12:54:35:ST3_smx:INFO: chip: 19-4 37.726682 C 1171.483840 mV
12:54:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:35:ST3_smx:INFO: Electrons
12:54:35:ST3_smx:INFO: # loops 0
12:54:38:ST3_smx:INFO: # loops 1
12:54:39:ST3_smx:INFO: # loops 2
12:54:42:ST3_smx:INFO: Total # of broken channels: 0
12:54:42:ST3_smx:INFO: List of broken channels: []
12:54:42:ST3_smx:INFO: Total # of broken channels: 0
12:54:42:ST3_smx:INFO: List of broken channels: []
12:54:43:ST3_smx:INFO: chip: 26-5 15.590880 C 1265.400000 mV
12:54:43:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:43:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:43:ST3_smx:INFO: Electrons
12:54:43:ST3_smx:INFO: # loops 0
12:54:45:ST3_smx:INFO: # loops 1
12:54:48:ST3_smx:INFO: # loops 2
12:54:50:ST3_smx:INFO: Total # of broken channels: 0
12:54:50:ST3_smx:INFO: List of broken channels: []
12:54:50:ST3_smx:INFO: Total # of broken channels: 0
12:54:50:ST3_smx:INFO: List of broken channels: []
12:54:51:ST3_smx:INFO: chip: 17-6 25.062742 C 1224.468235 mV
12:54:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:51:ST3_smx:INFO: Electrons
12:54:51:ST3_smx:INFO: # loops 0
12:54:54:ST3_smx:INFO: # loops 1
12:54:56:ST3_smx:INFO: # loops 2
12:54:58:ST3_smx:INFO: Total # of broken channels: 0
12:54:58:ST3_smx:INFO: List of broken channels: []
12:54:58:ST3_smx:INFO: Total # of broken channels: 0
12:54:58:ST3_smx:INFO: List of broken channels: []
12:55:00:ST3_smx:INFO: chip: 24-7 37.726682 C 1183.292940 mV
12:55:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:55:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:55:00:ST3_smx:INFO: Electrons
12:55:00:ST3_smx:INFO: # loops 0
12:55:02:ST3_smx:INFO: # loops 1
12:55:04:ST3_smx:INFO: # loops 2
12:55:06:ST3_smx:INFO: Total # of broken channels: 0
12:55:06:ST3_smx:INFO: List of broken channels: []
12:55:06:ST3_smx:INFO: Total # of broken channels: 0
12:55:06:ST3_smx:INFO: List of broken channels: []
12:55:06:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:55:06:febtest:INFO: 23-00 | XA-000-08-003-000-002-071-02 | 34.6 | 1206.9
12:55:07:febtest:INFO: 30-01 | XA-000-08-003-000-002-077-02 | 37.7 | 1206.9
12:55:07:febtest:INFO: 21-02 | XA-000-08-003-000-002-079-02 | 31.4 | 1218.6
12:55:07:febtest:INFO: 28-03 | XA-000-08-003-000-002-072-02 | 40.9 | 1189.2
12:55:07:febtest:INFO: 19-04 | XA-000-08-003-000-002-074-02 | 40.9 | 1189.2
12:55:07:febtest:INFO: 26-05 | XA-000-08-003-000-002-080-05 | 18.7 | 1282.9
12:55:08:febtest:INFO: 17-06 | XA-000-08-003-000-002-070-02 | 25.1 | 1242.0
12:55:08:febtest:INFO: 24-07 | XA-000-08-003-000-002-076-02 | 37.7 | 1212.7
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_07_17-12_53_30
OPERATOR : Alois Alzheimer
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4052| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.8030', '1.849', '2.1840']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9510', '1.850', '2.5210']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9170', '1.850', '0.5115']