
FEB_4054 15.07.24 09:46:40
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09:46:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 09:46:40:ST3_Shared:INFO: FEB-Microcable 09:46:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 09:46:41:febtest:INFO: Testing FEB with SN 4054 09:46:42:smx_tester:INFO: Scanning setup 09:46:42:elinks:INFO: Disabling clock on downlink 0 09:46:42:elinks:INFO: Disabling clock on downlink 1 09:46:42:elinks:INFO: Disabling clock on downlink 2 09:46:42:elinks:INFO: Disabling clock on downlink 3 09:46:42:elinks:INFO: Disabling clock on downlink 4 09:46:42:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:46:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 09:46:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:46:42:elinks:INFO: Disabling clock on downlink 0 09:46:42:elinks:INFO: Disabling clock on downlink 1 09:46:42:elinks:INFO: Disabling clock on downlink 2 09:46:42:elinks:INFO: Disabling clock on downlink 3 09:46:42:elinks:INFO: Disabling clock on downlink 4 09:46:42:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:46:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 09:46:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:46:42:elinks:INFO: Disabling clock on downlink 0 09:46:42:elinks:INFO: Disabling clock on downlink 1 09:46:42:elinks:INFO: Disabling clock on downlink 2 09:46:42:elinks:INFO: Disabling clock on downlink 3 09:46:42:elinks:INFO: Disabling clock on downlink 4 09:46:42:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:46:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28 09:46:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29 09:46:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30 09:46:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31 09:46:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:46:43:elinks:INFO: Disabling clock on downlink 0 09:46:43:elinks:INFO: Disabling clock on downlink 1 09:46:43:elinks:INFO: Disabling clock on downlink 2 09:46:43:elinks:INFO: Disabling clock on downlink 3 09:46:43:elinks:INFO: Disabling clock on downlink 4 09:46:43:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:46:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 09:46:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:46:43:elinks:INFO: Disabling clock on downlink 0 09:46:43:elinks:INFO: Disabling clock on downlink 1 09:46:43:elinks:INFO: Disabling clock on downlink 2 09:46:43:elinks:INFO: Disabling clock on downlink 3 09:46:43:elinks:INFO: Disabling clock on downlink 4 09:46:43:setup_element:INFO: Checking SOS, encoding_mode: SOS 09:46:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 09:46:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 09:46:43:setup_element:INFO: Scanning clock phase 09:46:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:46:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:46:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2 09:46:43:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:46:43:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:46:43:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:46:43:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 09:46:43:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________XXXXXX____________ Clock Delay: 24 09:46:43:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________XXXXXX____________ Clock Delay: 24 09:46:43:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________ Clock Delay: 40 09:46:43:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________________ Clock Delay: 40 09:46:43:setup_element:INFO: Setting the clock phase to 25 for group 0, downlink 2 09:46:43:setup_element:INFO: Scanning data phases 09:46:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:46:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:46:48:setup_element:INFO: Data phase scan results for group 0, downlink 2 09:46:48:setup_element:INFO: Eye window for uplink 24: _____XXXXXXX____________________________ Data delay found: 28 09:46:48:setup_element:INFO: Eye window for uplink 25: ________XXXXXXX_________________________ Data delay found: 31 09:46:48:setup_element:INFO: Eye window for uplink 26: ____XXXXXXXXX___________________________ Data delay found: 28 09:46:48:setup_element:INFO: Eye window for uplink 27: _________XXXXXXXXXX_____________________ Data delay found: 33 09:46:48:setup_element:INFO: Eye window for uplink 28: __________XXXXXXX_______________________ Data delay found: 33 09:46:48:setup_element:INFO: Eye window for uplink 29: _____________XXXXXXXX___________________ Data delay found: 36 09:46:48:setup_element:INFO: Eye window for uplink 30: ___________XXXXXXX______________________ Data delay found: 34 09:46:48:setup_element:INFO: Eye window for uplink 31: ____________XXXXXX______________________ Data delay found: 34 09:46:48:setup_element:INFO: Setting the data phase to 28 for uplink 24 09:46:48:setup_element:INFO: Setting the data phase to 31 for uplink 25 09:46:48:setup_element:INFO: Setting the data phase to 28 for uplink 26 09:46:48:setup_element:INFO: Setting the data phase to 33 for uplink 27 09:46:48:setup_element:INFO: Setting the data phase to 33 for uplink 28 09:46:48:setup_element:INFO: Setting the data phase to 36 for uplink 29 09:46:48:setup_element:INFO: Setting the data phase to 34 for uplink 30 09:46:48:setup_element:INFO: Setting the data phase to 34 for uplink 31 09:46:48:setup_element:INFO: Beginning SMX ASICs map scan 09:46:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:46:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:46:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 09:46:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 09:46:48:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31] 09:46:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30 09:46:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31 09:46:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28 09:46:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29 09:46:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26 09:46:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27 09:46:49:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24 09:46:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25 09:46:51:setup_element:INFO: Performing Elink synchronization 09:46:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 09:46:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 09:46:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 09:46:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 09:46:51:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2 09:46:51:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31] |_________________________________________________________________________| _addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_ 1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)] 3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)] 5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)] 7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)] |_________________________________________________________________________| 09:46:51:febtest:INFO: Init all SMX (CSA): 30 09:46:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 09:46:59:febtest:INFO: 30-01 | XA-000-08-003-000-002-112-11 | 50.4 | 1112.1 09:46:59:febtest:INFO: 28-03 | XA-000-08-003-000-002-117-11 | 40.9 | 1147.8 09:46:59:febtest:INFO: 26-05 | XA-000-08-003-000-002-122-11 | 37.7 | 1159.7 09:46:59:febtest:INFO: 24-07 | XA-000-08-003-000-002-111-12 | 31.4 | 1183.3 09:47:00:febtest:INFO: Set all CSA to ZERO FEB type: B FEB_A: 0 FEB_B: 1 09:47:02:ST3_smx:INFO: chip: 30-1 50.430383 C 1124.048640 mV 09:47:02:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:02:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:02:ST3_smx:INFO: Electrons 09:47:02:ST3_smx:INFO: # loops 0 09:47:04:ST3_smx:INFO: # loops 1 09:47:06:ST3_smx:INFO: # loops 2 09:47:07:ST3_smx:INFO: Total # of broken channels: 0 09:47:07:ST3_smx:INFO: List of broken channels: [] 09:47:07:ST3_smx:INFO: Total # of broken channels: 0 09:47:07:ST3_smx:INFO: List of broken channels: [] 09:47:09:ST3_smx:INFO: chip: 28-3 40.898880 C 1159.654860 mV 09:47:09:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:09:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:09:ST3_smx:INFO: Electrons 09:47:09:ST3_smx:INFO: # loops 0 09:47:11:ST3_smx:INFO: # loops 1 09:47:12:ST3_smx:INFO: # loops 2 09:47:14:ST3_smx:INFO: Total # of broken channels: 0 09:47:14:ST3_smx:INFO: List of broken channels: [] 09:47:14:ST3_smx:INFO: Total # of broken channels: 0 09:47:14:ST3_smx:INFO: List of broken channels: [] 09:47:15:ST3_smx:INFO: chip: 26-5 37.726682 C 1171.483840 mV 09:47:15:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:15:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:15:ST3_smx:INFO: Electrons 09:47:15:ST3_smx:INFO: # loops 0 09:47:17:ST3_smx:INFO: # loops 1 09:47:18:ST3_smx:INFO: # loops 2 09:47:20:ST3_smx:INFO: Total # of broken channels: 0 09:47:20:ST3_smx:INFO: List of broken channels: [] 09:47:20:ST3_smx:INFO: Total # of broken channels: 0 09:47:20:ST3_smx:INFO: List of broken channels: [] 09:47:22:ST3_smx:INFO: chip: 24-7 31.389742 C 1189.190035 mV 09:47:22:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:22:ST3_discr_histo:WARNING: Not enough entries for fit!!! 09:47:22:ST3_smx:INFO: Electrons 09:47:22:ST3_smx:INFO: # loops 0 09:47:23:ST3_smx:INFO: # loops 1 09:47:25:ST3_smx:INFO: # loops 2 09:47:27:ST3_smx:INFO: Total # of broken channels: 0 09:47:27:ST3_smx:INFO: List of broken channels: [] 09:47:27:ST3_smx:INFO: Total # of broken channels: 0 09:47:27:ST3_smx:INFO: List of broken channels: [] 09:47:27:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 09:47:27:febtest:INFO: 30-01 | XA-000-08-003-000-002-112-11 | 50.4 | 1141.9 09:47:27:febtest:INFO: 28-03 | XA-000-08-003-000-002-117-11 | 40.9 | 1183.3 09:47:27:febtest:INFO: 26-05 | XA-000-08-003-000-002-122-11 | 37.7 | 1195.1 09:47:28:febtest:INFO: 24-07 | XA-000-08-003-000-002-111-12 | 31.4 | 1206.9 ############################################################ # S U M M A R Y # ############################################################ {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Microcable TEST_DATE : 24_07_15-09_46_40 OPERATOR : Benjamin; SITE : KIT | SETUP : KIT_TEST_SETUP_1 ------------------------------------------------------------ | FEB_SN : 4054| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B ------------------------------------------------------------ ------------------------------------------------------------ VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.452', '0.8281', '1.850', '1.1980'] VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0200', '1.850', '1.3230'] VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9908', '1.850', '0.2687']