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FEB_4069 13.08.24 09:45:12
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09:45:12:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:45:12:ST3_Shared:INFO: FEB-Microcable
09:45:12:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:45:12:febtest:INFO: Testing FEB with SN 4069
09:45:14:smx_tester:INFO: Scanning setup
09:45:14:elinks:INFO: Disabling clock on downlink 0
09:45:14:elinks:INFO: Disabling clock on downlink 1
09:45:14:elinks:INFO: Disabling clock on downlink 2
09:45:14:elinks:INFO: Disabling clock on downlink 3
09:45:14:elinks:INFO: Disabling clock on downlink 4
09:45:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:45:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
09:45:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:45:14:elinks:INFO: Disabling clock on downlink 0
09:45:14:elinks:INFO: Disabling clock on downlink 1
09:45:14:elinks:INFO: Disabling clock on downlink 2
09:45:14:elinks:INFO: Disabling clock on downlink 3
09:45:14:elinks:INFO: Disabling clock on downlink 4
09:45:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:45:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:45:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:45:14:elinks:INFO: Disabling clock on downlink 0
09:45:14:elinks:INFO: Disabling clock on downlink 1
09:45:14:elinks:INFO: Disabling clock on downlink 2
09:45:14:elinks:INFO: Disabling clock on downlink 3
09:45:14:elinks:INFO: Disabling clock on downlink 4
09:45:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:45:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
09:45:14:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
09:45:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:45:14:elinks:INFO: Disabling clock on downlink 0
09:45:14:elinks:INFO: Disabling clock on downlink 1
09:45:14:elinks:INFO: Disabling clock on downlink 2
09:45:14:elinks:INFO: Disabling clock on downlink 3
09:45:14:elinks:INFO: Disabling clock on downlink 4
09:45:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:45:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
09:45:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:45:15:elinks:INFO: Disabling clock on downlink 0
09:45:15:elinks:INFO: Disabling clock on downlink 1
09:45:15:elinks:INFO: Disabling clock on downlink 2
09:45:15:elinks:INFO: Disabling clock on downlink 3
09:45:15:elinks:INFO: Disabling clock on downlink 4
09:45:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:45:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
09:45:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:45:15:setup_element:INFO: Scanning clock phase
09:45:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:45:15:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:45:15:setup_element:INFO: Clock phase scan results for group 0, downlink 2
09:45:15:setup_element:INFO: Eye window for uplink 24: ________________________________________________________________________________
Clock Delay: 40
09:45:15:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________________
Clock Delay: 40
09:45:15:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________XXXXXXX_________
Clock Delay: 27
09:45:15:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________XXXXXXX_________
Clock Delay: 27
09:45:15:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________XXXXXXXX_________
Clock Delay: 26
09:45:15:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________XXXXXXXX_________
Clock Delay: 26
09:45:15:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
09:45:15:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
09:45:15:setup_element:INFO: Setting the clock phase to 26 for group 0, downlink 2
09:45:15:setup_element:INFO: Scanning data phases
09:45:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:45:15:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:45:20:setup_element:INFO: Data phase scan results for group 0, downlink 2
09:45:20:setup_element:INFO: Eye window for uplink 24: _____XXXXXX_____________________________
Data delay found: 27
09:45:20:setup_element:INFO: Eye window for uplink 25: ________XXXXXX__________________________
Data delay found: 30
09:45:20:setup_element:INFO: Eye window for uplink 26: ______XXXXXXX___________________________
Data delay found: 29
09:45:20:setup_element:INFO: Eye window for uplink 27: __________XXXXXXXXX_____________________
Data delay found: 34
09:45:20:setup_element:INFO: Eye window for uplink 28: __________XXXXXXXXX_____________________
Data delay found: 34
09:45:20:setup_element:INFO: Eye window for uplink 29: _____________XXXXXXXXX__________________
Data delay found: 37
09:45:20:setup_element:INFO: Eye window for uplink 30: ___________XXXXXXX______________________
Data delay found: 34
09:45:20:setup_element:INFO: Eye window for uplink 31: _____________XXXXX______________________
Data delay found: 35
09:45:20:setup_element:INFO: Setting the data phase to 27 for uplink 24
09:45:20:setup_element:INFO: Setting the data phase to 30 for uplink 25
09:45:20:setup_element:INFO: Setting the data phase to 29 for uplink 26
09:45:20:setup_element:INFO: Setting the data phase to 34 for uplink 27
09:45:20:setup_element:INFO: Setting the data phase to 34 for uplink 28
09:45:20:setup_element:INFO: Setting the data phase to 37 for uplink 29
09:45:20:setup_element:INFO: Setting the data phase to 34 for uplink 30
09:45:20:setup_element:INFO: Setting the data phase to 35 for uplink 31
09:45:20:setup_element:INFO: Beginning SMX ASICs map scan
09:45:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:45:20:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:45:20:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
09:45:20:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
09:45:20:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
09:45:20:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:45:20:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:45:21:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:45:21:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:45:21:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:45:21:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:45:21:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:45:21:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:45:23:setup_element:INFO: Performing Elink synchronization
09:45:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:45:23:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:45:23:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
09:45:23:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
09:45:23:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
09:45:23:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
09:45:23:febtest:INFO: Init all SMX (CSA): 30
09:45:30:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:45:31:febtest:INFO: 30-01 | XA-000-08-003-000-004-246-04 | 37.7 | 1171.5
09:45:31:febtest:INFO: 28-03 | XA-000-08-003-000-004-245-04 | 31.4 | 1189.2
09:45:31:febtest:INFO: 26-05 | XA-000-08-003-000-004-244-04 | 40.9 | 1159.7
09:45:31:febtest:INFO: 24-07 | XA-000-08-003-000-004-242-04 | 21.9 | 1218.6
09:45:32:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
09:45:34:ST3_smx:INFO: chip: 30-1 37.726682 C 1183.292940 mV
09:45:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:34:ST3_smx:INFO: Electrons
09:45:34:ST3_smx:INFO: # loops 0
09:45:36:ST3_smx:INFO: # loops 1
09:45:37:ST3_smx:INFO: # loops 2
09:45:39:ST3_smx:INFO: Total # of broken channels: 0
09:45:39:ST3_smx:INFO: List of broken channels: []
09:45:39:ST3_smx:INFO: Total # of broken channels: 0
09:45:39:ST3_smx:INFO: List of broken channels: []
09:45:41:ST3_smx:INFO: chip: 28-3 31.389742 C 1200.969315 mV
09:45:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:41:ST3_smx:INFO: Electrons
09:45:41:ST3_smx:INFO: # loops 0
09:45:42:ST3_smx:INFO: # loops 1
09:45:44:ST3_smx:INFO: # loops 2
09:45:45:ST3_smx:INFO: Total # of broken channels: 0
09:45:45:ST3_smx:INFO: List of broken channels: []
09:45:45:ST3_smx:INFO: Total # of broken channels: 0
09:45:45:ST3_smx:INFO: List of broken channels: []
09:45:47:ST3_smx:INFO: chip: 26-5 40.898880 C 1165.571835 mV
09:45:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:47:ST3_smx:INFO: Electrons
09:45:47:ST3_smx:INFO: # loops 0
09:45:48:ST3_smx:INFO: # loops 1
09:45:50:ST3_smx:INFO: # loops 2
09:45:51:ST3_smx:INFO: Total # of broken channels: 0
09:45:51:ST3_smx:INFO: List of broken channels: []
09:45:51:ST3_smx:INFO: Total # of broken channels: 0
09:45:51:ST3_smx:INFO: List of broken channels: []
09:45:53:ST3_smx:INFO: chip: 24-7 21.902970 C 1230.330540 mV
09:45:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:45:53:ST3_smx:INFO: Electrons
09:45:53:ST3_smx:INFO: # loops 0
09:45:55:ST3_smx:INFO: # loops 1
09:45:56:ST3_smx:INFO: # loops 2
09:45:58:ST3_smx:INFO: Total # of broken channels: 0
09:45:58:ST3_smx:INFO: List of broken channels: []
09:45:58:ST3_smx:INFO: Total # of broken channels: 0
09:45:58:ST3_smx:INFO: List of broken channels: []
09:45:58:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:45:58:febtest:INFO: 30-01 | XA-000-08-003-000-004-246-04 | 40.9 | 1201.0
09:45:58:febtest:INFO: 28-03 | XA-000-08-003-000-004-245-04 | 34.6 | 1218.6
09:45:59:febtest:INFO: 26-05 | XA-000-08-003-000-004-244-04 | 40.9 | 1189.2
09:45:59:febtest:INFO: 24-07 | XA-000-08-003-000-004-242-04 | 25.1 | 1247.9
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_08_13-09_45_12
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4069| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7718', '1.850', '1.1170']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0120', '1.850', '1.2970']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9944', '1.850', '0.2705']