
FEB_4080 24.09.24 07:52:49
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07:52:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 07:52:49:ST3_Shared:INFO: FEB-Microcable 07:52:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 07:52:49:febtest:INFO: Testing FEB with SN 4080 07:52:51:smx_tester:INFO: Scanning setup 07:52:51:elinks:INFO: Disabling clock on downlink 0 07:52:51:elinks:INFO: Disabling clock on downlink 1 07:52:51:elinks:INFO: Disabling clock on downlink 2 07:52:51:elinks:INFO: Disabling clock on downlink 3 07:52:51:elinks:INFO: Disabling clock on downlink 4 07:52:51:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 07:52:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:52:51:elinks:INFO: Disabling clock on downlink 0 07:52:51:elinks:INFO: Disabling clock on downlink 1 07:52:51:elinks:INFO: Disabling clock on downlink 2 07:52:51:elinks:INFO: Disabling clock on downlink 3 07:52:51:elinks:INFO: Disabling clock on downlink 4 07:52:51:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:52:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:52:51:elinks:INFO: Disabling clock on downlink 0 07:52:51:elinks:INFO: Disabling clock on downlink 1 07:52:51:elinks:INFO: Disabling clock on downlink 2 07:52:51:elinks:INFO: Disabling clock on downlink 3 07:52:51:elinks:INFO: Disabling clock on downlink 4 07:52:51:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30 07:52:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31 07:52:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:52:51:elinks:INFO: Disabling clock on downlink 0 07:52:51:elinks:INFO: Disabling clock on downlink 1 07:52:51:elinks:INFO: Disabling clock on downlink 2 07:52:51:elinks:INFO: Disabling clock on downlink 3 07:52:51:elinks:INFO: Disabling clock on downlink 4 07:52:51:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 07:52:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:52:51:elinks:INFO: Disabling clock on downlink 0 07:52:51:elinks:INFO: Disabling clock on downlink 1 07:52:51:elinks:INFO: Disabling clock on downlink 2 07:52:51:elinks:INFO: Disabling clock on downlink 3 07:52:51:elinks:INFO: Disabling clock on downlink 4 07:52:51:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 07:52:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:52:51:setup_element:INFO: Scanning clock phase 07:52:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:52:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 07:52:52:setup_element:INFO: Clock phase scan results for group 0, downlink 2 07:52:52:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXX________ Clock Delay: 28 07:52:52:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXX________ Clock Delay: 28 07:52:52:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________XXXXXXXX________ Clock Delay: 27 07:52:52:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________XXXXXXXX________ Clock Delay: 27 07:52:52:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________XXXXXX__________ Clock Delay: 26 07:52:52:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________XXXXXX__________ Clock Delay: 26 07:52:52:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 07:52:52:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________XXXXXXX__________ Clock Delay: 26 07:52:52:setup_element:INFO: Setting the clock phase to 27 for group 0, downlink 2 07:52:52:setup_element:INFO: Scanning data phases 07:52:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:52:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 07:52:57:setup_element:INFO: Data phase scan results for group 0, downlink 2 07:52:57:setup_element:INFO: Eye window for uplink 24: ________XXXXXXX_________________________ Data delay found: 31 07:52:57:setup_element:INFO: Eye window for uplink 25: ____________XXXXXXX_____________________ Data delay found: 35 07:52:57:setup_element:INFO: Eye window for uplink 26: ________XXXXXXX_________________________ Data delay found: 31 07:52:57:setup_element:INFO: Eye window for uplink 27: _____________XXXXXXX____________________ Data delay found: 36 07:52:57:setup_element:INFO: Eye window for uplink 28: _______________XXXXXX___________________ Data delay found: 37 07:52:57:setup_element:INFO: Eye window for uplink 29: __________________XXXXXX________________ Data delay found: 0 07:52:57:setup_element:INFO: Eye window for uplink 30: ____________XXXXXXXXXX__________________ Data delay found: 36 07:52:57:setup_element:INFO: Eye window for uplink 31: _____________XXXXXXXXX__________________ Data delay found: 37 07:52:57:setup_element:INFO: Setting the data phase to 31 for uplink 24 07:52:57:setup_element:INFO: Setting the data phase to 35 for uplink 25 07:52:57:setup_element:INFO: Setting the data phase to 31 for uplink 26 07:52:57:setup_element:INFO: Setting the data phase to 36 for uplink 27 07:52:57:setup_element:INFO: Setting the data phase to 37 for uplink 28 07:52:57:setup_element:INFO: Setting the data phase to 0 for uplink 29 07:52:57:setup_element:INFO: Setting the data phase to 36 for uplink 30 07:52:57:setup_element:INFO: Setting the data phase to 37 for uplink 31 07:52:57:setup_element:INFO: Beginning SMX ASICs map scan 07:52:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:52:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 07:52:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 07:52:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 07:52:57:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31] 07:52:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30 07:52:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31 07:52:57:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28 07:52:57:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29 07:52:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26 07:52:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27 07:52:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24 07:52:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25 07:52:59:setup_element:INFO: Performing Elink synchronization 07:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:52:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 07:52:59:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 07:52:59:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 07:52:59:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2 07:52:59:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31] |_________________________________________________________________________| _addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_ 1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)] 3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)] 5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)] 7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)] |_________________________________________________________________________| 07:53:00:febtest:INFO: Init all SMX (CSA): 30 07:53:07:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 07:53:07:febtest:INFO: 30-01 | XA-000-08-003-000-005-217-07 | 25.1 | 1201.0 07:53:08:febtest:INFO: 28-03 | XA-000-08-003-000-005-170-11 | 34.6 | 1159.7 07:53:08:febtest:INFO: 26-05 | XA-000-08-003-000-005-173-11 | 12.4 | 1230.3 07:53:08:febtest:INFO: 24-07 | XA-000-08-003-000-005-179-12 | 15.6 | 1392.5 07:53:09:febtest:INFO: Set all CSA to ZERO FEB type: B FEB_A: 0 FEB_B: 1 07:53:11:ST3_smx:INFO: chip: 30-1 25.062742 C 1206.851500 mV 07:53:11:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:11:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:11:ST3_smx:INFO: Electrons 07:53:11:ST3_smx:INFO: # loops 0 07:53:13:ST3_smx:INFO: # loops 1 07:53:14:ST3_smx:INFO: # loops 2 07:53:16:ST3_smx:INFO: Total # of broken channels: 0 07:53:16:ST3_smx:INFO: List of broken channels: [] 07:53:16:ST3_smx:INFO: Total # of broken channels: 0 07:53:16:ST3_smx:INFO: List of broken channels: [] 07:53:18:ST3_smx:INFO: chip: 28-3 37.726682 C 1165.571835 mV 07:53:18:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:18:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:18:ST3_smx:INFO: Electrons 07:53:18:ST3_smx:INFO: # loops 0 07:53:19:ST3_smx:INFO: # loops 1 07:53:21:ST3_smx:INFO: # loops 2 07:53:22:ST3_smx:INFO: Total # of broken channels: 0 07:53:22:ST3_smx:INFO: List of broken channels: [] 07:53:22:ST3_smx:INFO: Total # of broken channels: 0 07:53:22:ST3_smx:INFO: List of broken channels: [] 07:53:24:ST3_smx:INFO: chip: 26-5 12.438562 C 1242.040240 mV 07:53:24:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:24:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:24:ST3_smx:INFO: Electrons 07:53:24:ST3_smx:INFO: # loops 0 07:53:26:ST3_smx:INFO: # loops 1 07:53:27:ST3_smx:INFO: # loops 2 07:53:29:ST3_smx:INFO: Total # of broken channels: 0 07:53:29:ST3_smx:INFO: List of broken channels: [] 07:53:29:ST3_smx:INFO: Total # of broken channels: 0 07:53:29:ST3_smx:INFO: List of broken channels: [] 07:53:30:ST3_smx:INFO: chip: 24-7 12.438562 C 1578.532875 mV 07:53:30:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:30:ST3_discr_histo:WARNING: Not enough entries for fit!!! 07:53:30:ST3_smx:INFO: Electrons 07:53:30:ST3_smx:INFO: # loops 0 07:53:32:ST3_smx:INFO: # loops 1 07:53:33:ST3_smx:INFO: # loops 2 07:53:35:ST3_smx:INFO: Total # of broken channels: 0 07:53:35:ST3_smx:INFO: List of broken channels: [] 07:53:35:ST3_smx:INFO: Total # of broken channels: 0 07:53:35:ST3_smx:INFO: List of broken channels: [] 07:53:35:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 07:53:36:febtest:INFO: 30-01 | XA-000-08-003-000-005-217-07 | 25.1 | 1230.3 07:53:36:febtest:INFO: 28-03 | XA-000-08-003-000-005-170-11 | 37.7 | 1189.2 07:53:36:febtest:INFO: 26-05 | XA-000-08-003-000-005-173-11 | 15.6 | 1265.4 07:53:36:febtest:INFO: 24-07 | XA-000-08-003-000-005-179-12 | 9.3 | 1578.5 ############################################################ # S U M M A R Y # ############################################################ {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Microcable TEST_DATE : 24_09_24-07_52_49 OPERATOR : Benjamin; SITE : KIT | SETUP : KIT_TEST_SETUP_1 ------------------------------------------------------------ | FEB_SN : 4080| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B ------------------------------------------------------------ ------------------------------------------------------------ VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.453', '0.8216', '1.850', '1.3800'] VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0310', '1.850', '1.3320'] VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0050', '1.850', '0.2702']