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FEB_4120 26.02.25 15:31:30
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15:31:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:31:30:ST3_Shared:INFO: FEB-Microcable
15:31:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:31:30:febtest:INFO: Testing FEB with SN 4120
15:31:32:smx_tester:INFO: Scanning setup
15:31:32:elinks:INFO: Disabling clock on downlink 0
15:31:32:elinks:INFO: Disabling clock on downlink 1
15:31:32:elinks:INFO: Disabling clock on downlink 2
15:31:32:elinks:INFO: Disabling clock on downlink 3
15:31:32:elinks:INFO: Disabling clock on downlink 4
15:31:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:31:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:31:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:31:32:elinks:INFO: Disabling clock on downlink 0
15:31:32:elinks:INFO: Disabling clock on downlink 1
15:31:32:elinks:INFO: Disabling clock on downlink 2
15:31:32:elinks:INFO: Disabling clock on downlink 3
15:31:32:elinks:INFO: Disabling clock on downlink 4
15:31:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:31:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:31:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:31:32:elinks:INFO: Disabling clock on downlink 0
15:31:32:elinks:INFO: Disabling clock on downlink 1
15:31:32:elinks:INFO: Disabling clock on downlink 2
15:31:32:elinks:INFO: Disabling clock on downlink 3
15:31:32:elinks:INFO: Disabling clock on downlink 4
15:31:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:31:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:31:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:31:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:31:32:elinks:INFO: Disabling clock on downlink 0
15:31:32:elinks:INFO: Disabling clock on downlink 1
15:31:32:elinks:INFO: Disabling clock on downlink 2
15:31:32:elinks:INFO: Disabling clock on downlink 3
15:31:32:elinks:INFO: Disabling clock on downlink 4
15:31:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:31:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:31:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:31:32:elinks:INFO: Disabling clock on downlink 0
15:31:32:elinks:INFO: Disabling clock on downlink 1
15:31:33:elinks:INFO: Disabling clock on downlink 2
15:31:33:elinks:INFO: Disabling clock on downlink 3
15:31:33:elinks:INFO: Disabling clock on downlink 4
15:31:33:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:31:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:31:33:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:31:33:setup_element:INFO: Scanning clock phase
15:31:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:31:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:31:33:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:31:33:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:31:33:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:31:33:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________XXXXX___
Clock Delay: 34
15:31:33:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________XXXXX___
Clock Delay: 34
15:31:33:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXX____
Clock Delay: 33
15:31:33:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXX____
Clock Delay: 33
15:31:33:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXX_____
Clock Delay: 32
15:31:33:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXX_____
Clock Delay: 32
15:31:33:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
15:31:33:setup_element:INFO: Scanning data phases
15:31:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:31:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:31:38:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:31:38:setup_element:INFO: Eye window for uplink 24: _______XXXXX____________________________
Data delay found: 29
15:31:38:setup_element:INFO: Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
15:31:38:setup_element:INFO: Eye window for uplink 26: _______XXXXXX___________________________
Data delay found: 29
15:31:38:setup_element:INFO: Eye window for uplink 27: ___________XXXXXXX______________________
Data delay found: 34
15:31:38:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
15:31:38:setup_element:INFO: Eye window for uplink 29: _____________XXXXX______________________
Data delay found: 35
15:31:38:setup_element:INFO: Eye window for uplink 30: ___________XXXXXX_______________________
Data delay found: 33
15:31:38:setup_element:INFO: Eye window for uplink 31: ____________XXXX________________________
Data delay found: 33
15:31:38:setup_element:INFO: Setting the data phase to 29 for uplink 24
15:31:38:setup_element:INFO: Setting the data phase to 32 for uplink 25
15:31:38:setup_element:INFO: Setting the data phase to 29 for uplink 26
15:31:38:setup_element:INFO: Setting the data phase to 34 for uplink 27
15:31:38:setup_element:INFO: Setting the data phase to 33 for uplink 28
15:31:38:setup_element:INFO: Setting the data phase to 35 for uplink 29
15:31:38:setup_element:INFO: Setting the data phase to 33 for uplink 30
15:31:38:setup_element:INFO: Setting the data phase to 33 for uplink 31
15:31:38:setup_element:INFO: Beginning SMX ASICs map scan
15:31:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:31:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:31:38:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:31:38:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:31:38:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
15:31:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:31:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:31:39:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:31:39:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:31:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:31:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:31:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:31:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:31:41:setup_element:INFO: Performing Elink synchronization
15:31:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:31:41:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:31:41:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:31:41:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:31:41:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:31:41:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
15:31:41:febtest:INFO: Init all SMX (CSA): 30
15:31:48:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:31:48:febtest:INFO: 30-01 | XA-000-09-004-005-010-021-15 | 47.3 | 1130.0
15:31:49:febtest:INFO: 28-03 | XA-000-09-004-005-004-021-06 | 31.4 | 1183.3
15:31:49:febtest:INFO: 26-05 | XA-000-09-004-005-004-020-06 | 31.4 | 1183.3
15:31:49:febtest:INFO: 24-07 | XA-000-09-004-005-007-025-08 | 47.3 | 1124.0
15:31:50:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
15:31:52:ST3_smx:INFO: chip: 30-1 47.250730 C 1141.874115 mV
15:31:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:31:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:31:52:ST3_smx:INFO: Electrons
15:31:52:ST3_smx:INFO: # loops 0
15:31:54:ST3_smx:INFO: # loops 1
15:31:55:ST3_smx:INFO: # loops 2
15:31:57:ST3_smx:INFO: Total # of broken channels: 0
15:31:57:ST3_smx:INFO: List of broken channels: []
15:31:57:ST3_smx:INFO: Total # of broken channels: 0
15:31:57:ST3_smx:INFO: List of broken channels: []
15:31:58:ST3_smx:INFO: chip: 28-3 31.389742 C 1195.082160 mV
15:31:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:31:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:31:58:ST3_smx:INFO: Electrons
15:31:58:ST3_smx:INFO: # loops 0
15:32:00:ST3_smx:INFO: # loops 1
15:32:02:ST3_smx:INFO: # loops 2
15:32:03:ST3_smx:INFO: Total # of broken channels: 0
15:32:03:ST3_smx:INFO: List of broken channels: []
15:32:03:ST3_smx:INFO: Total # of broken channels: 0
15:32:03:ST3_smx:INFO: List of broken channels: []
15:32:05:ST3_smx:INFO: chip: 26-5 31.389742 C 1195.082160 mV
15:32:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:32:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:32:05:ST3_smx:INFO: Electrons
15:32:05:ST3_smx:INFO: # loops 0
15:32:06:ST3_smx:INFO: # loops 1
15:32:08:ST3_smx:INFO: # loops 2
15:32:09:ST3_smx:INFO: Total # of broken channels: 0
15:32:09:ST3_smx:INFO: List of broken channels: []
15:32:09:ST3_smx:INFO: Total # of broken channels: 0
15:32:09:ST3_smx:INFO: List of broken channels: []
15:32:11:ST3_smx:INFO: chip: 24-7 50.430383 C 1135.937260 mV
15:32:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:32:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
15:32:11:ST3_smx:INFO: Electrons
15:32:11:ST3_smx:INFO: # loops 0
15:32:12:ST3_smx:INFO: # loops 1
15:32:14:ST3_smx:INFO: # loops 2
15:32:16:ST3_smx:INFO: Total # of broken channels: 0
15:32:16:ST3_smx:INFO: List of broken channels: []
15:32:16:ST3_smx:INFO: Total # of broken channels: 0
15:32:16:ST3_smx:INFO: List of broken channels: []
15:32:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:32:16:febtest:INFO: 30-01 | XA-000-09-004-005-010-021-15 | 47.3 | 1159.7
15:32:17:febtest:INFO: 28-03 | XA-000-09-004-005-004-021-06 | 31.4 | 1218.6
15:32:17:febtest:INFO: 26-05 | XA-000-09-004-005-004-020-06 | 34.6 | 1212.7
15:32:17:febtest:INFO: 24-07 | XA-000-09-004-005-007-025-08 | 50.4 | 1153.7
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_02_26-15_31_30
OPERATOR : Henrik;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4120| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7089', '1.850', '1.4910']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9916', '1.850', '1.3290']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9931', '1.851', '0.2677']