FEB_4130 24.03.25 14:17:33
Info
14:17:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:33:ST3_Shared:INFO: FEB-Microcable
14:17:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:33:febtest:INFO: Testing FEB with SN 4130
14:17:35:smx_tester:INFO: Scanning setup
14:17:35:elinks:INFO: Disabling clock on downlink 0
14:17:35:elinks:INFO: Disabling clock on downlink 1
14:17:35:elinks:INFO: Disabling clock on downlink 2
14:17:35:elinks:INFO: Disabling clock on downlink 3
14:17:35:elinks:INFO: Disabling clock on downlink 4
14:17:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:17:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:35:elinks:INFO: Disabling clock on downlink 0
14:17:35:elinks:INFO: Disabling clock on downlink 1
14:17:35:elinks:INFO: Disabling clock on downlink 2
14:17:35:elinks:INFO: Disabling clock on downlink 3
14:17:35:elinks:INFO: Disabling clock on downlink 4
14:17:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:17:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:35:elinks:INFO: Disabling clock on downlink 0
14:17:35:elinks:INFO: Disabling clock on downlink 1
14:17:35:elinks:INFO: Disabling clock on downlink 2
14:17:35:elinks:INFO: Disabling clock on downlink 3
14:17:35:elinks:INFO: Disabling clock on downlink 4
14:17:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:17:35:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:17:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:35:elinks:INFO: Disabling clock on downlink 0
14:17:35:elinks:INFO: Disabling clock on downlink 1
14:17:35:elinks:INFO: Disabling clock on downlink 2
14:17:35:elinks:INFO: Disabling clock on downlink 3
14:17:35:elinks:INFO: Disabling clock on downlink 4
14:17:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:35:elinks:INFO: Disabling clock on downlink 0
14:17:35:elinks:INFO: Disabling clock on downlink 1
14:17:35:elinks:INFO: Disabling clock on downlink 2
14:17:35:elinks:INFO: Disabling clock on downlink 3
14:17:35:elinks:INFO: Disabling clock on downlink 4
14:17:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:17:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:35:setup_element:INFO: Scanning clock phase
14:17:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:17:36:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:17:36:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXX____
Clock Delay: 32
14:17:36:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXX____
Clock Delay: 32
14:17:36:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXX_____
Clock Delay: 32
14:17:36:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXX_____
Clock Delay: 32
14:17:36:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:17:36:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:17:36:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXX_____
Clock Delay: 32
14:17:36:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXX_____
Clock Delay: 32
14:17:36:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
14:17:36:setup_element:INFO: Scanning data phases
14:17:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:17:41:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:17:41:setup_element:INFO: Eye window for uplink 24: _____XXXXX______________________________
Data delay found: 27
14:17:41:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
14:17:41:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________
Data delay found: 27
14:17:41:setup_element:INFO: Eye window for uplink 27: _________XXXXXXX________________________
Data delay found: 32
14:17:41:setup_element:INFO: Eye window for uplink 28: ______________XXXXX_____________________
Data delay found: 36
14:17:41:setup_element:INFO: Eye window for uplink 29: _________________XXXX___________________
Data delay found: 38
14:17:41:setup_element:INFO: Eye window for uplink 30: ____________XXXXXXX_____________________
Data delay found: 35
14:17:41:setup_element:INFO: Eye window for uplink 31: ______________XXX_______________________
Data delay found: 35
14:17:41:setup_element:INFO: Setting the data phase to 27 for uplink 24
14:17:41:setup_element:INFO: Setting the data phase to 30 for uplink 25
14:17:41:setup_element:INFO: Setting the data phase to 27 for uplink 26
14:17:41:setup_element:INFO: Setting the data phase to 32 for uplink 27
14:17:41:setup_element:INFO: Setting the data phase to 36 for uplink 28
14:17:41:setup_element:INFO: Setting the data phase to 38 for uplink 29
14:17:41:setup_element:INFO: Setting the data phase to 35 for uplink 30
14:17:41:setup_element:INFO: Setting the data phase to 35 for uplink 31
14:17:41:setup_element:INFO: Beginning SMX ASICs map scan
14:17:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:41:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:17:41:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:17:41:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:17:41:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:17:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:17:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:17:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:17:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:17:42:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:17:42:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:17:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:17:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:17:43:setup_element:INFO: Performing Elink synchronization
14:17:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:17:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:17:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:17:43:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:17:43:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:17:44:febtest:INFO: Init all SMX (CSA): 30
14:17:52:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:17:52:febtest:INFO: 30-01 | XA-000-09-004-005-009-021-01 | 18.7 | 1212.7
14:17:52:febtest:INFO: 28-03 | XA-000-09-004-005-015-023-04 | 25.1 | 1189.2
14:17:52:febtest:INFO: 26-05 | XA-000-09-004-005-015-021-04 | 15.6 | 1230.3
14:17:52:febtest:INFO: 24-07 | XA-000-09-004-005-006-021-05 | 40.9 | 1141.9
14:17:53:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:17:55:ST3_smx:INFO: chip: 30-1 21.902970 C 1224.468235 mV
14:17:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:17:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:17:55:ST3_smx:INFO: Electrons
14:17:55:ST3_smx:INFO: # loops 0
14:17:58:ST3_smx:INFO: # loops 1
14:17:59:ST3_smx:INFO: # loops 2
14:18:01:ST3_smx:INFO: Total # of broken channels: 0
14:18:01:ST3_smx:INFO: List of broken channels: []
14:18:01:ST3_smx:INFO: Total # of broken channels: 0
14:18:01:ST3_smx:INFO: List of broken channels: []
14:18:03:ST3_smx:INFO: chip: 28-3 25.062742 C 1206.851500 mV
14:18:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:03:ST3_smx:INFO: Electrons
14:18:03:ST3_smx:INFO: # loops 0
14:18:05:ST3_smx:INFO: # loops 1
14:18:06:ST3_smx:INFO: # loops 2
14:18:08:ST3_smx:INFO: Total # of broken channels: 0
14:18:08:ST3_smx:INFO: List of broken channels: []
14:18:08:ST3_smx:INFO: Total # of broken channels: 0
14:18:08:ST3_smx:INFO: List of broken channels: []
14:18:09:ST3_smx:INFO: chip: 26-5 15.590880 C 1242.040240 mV
14:18:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:09:ST3_smx:INFO: Electrons
14:18:09:ST3_smx:INFO: # loops 0
14:18:11:ST3_smx:INFO: # loops 1
14:18:13:ST3_smx:INFO: # loops 2
14:18:14:ST3_smx:INFO: Total # of broken channels: 0
14:18:14:ST3_smx:INFO: List of broken channels: []
14:18:14:ST3_smx:INFO: Total # of broken channels: 0
14:18:14:ST3_smx:INFO: List of broken channels: []
14:18:16:ST3_smx:INFO: chip: 24-7 44.073563 C 1147.806000 mV
14:18:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:16:ST3_smx:INFO: Electrons
14:18:16:ST3_smx:INFO: # loops 0
14:18:17:ST3_smx:INFO: # loops 1
14:18:19:ST3_smx:INFO: # loops 2
14:18:21:ST3_smx:INFO: Total # of broken channels: 0
14:18:21:ST3_smx:INFO: List of broken channels: []
14:18:21:ST3_smx:INFO: Total # of broken channels: 0
14:18:21:ST3_smx:INFO: List of broken channels: []
14:18:21:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:18:21:febtest:INFO: 30-01 | XA-000-09-004-005-009-021-01 | 21.9 | 1242.0
14:18:22:febtest:INFO: 28-03 | XA-000-09-004-005-015-023-04 | 25.1 | 1230.3
14:18:22:febtest:INFO: 26-05 | XA-000-09-004-005-015-021-04 | 15.6 | 1265.4
14:18:22:febtest:INFO: 24-07 | XA-000-09-004-005-006-021-05 | 44.1 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_03_24-14_17_33
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4130| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.452', '0.8154', '1.850', '1.0160']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9817', '1.850', '1.2910']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9736', '1.850', '0.2604']