Go Back
FEB_4170 11.06.25 07:40:35
TextEdit.txt
07:40:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:40:35:ST3_Shared:INFO: FEB-Microcable
07:40:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:40:36:febtest:INFO: Testing FEB with SN 4170
07:40:37:smx_tester:INFO: Scanning setup
07:40:37:elinks:INFO: Disabling clock on downlink 0
07:40:37:elinks:INFO: Disabling clock on downlink 1
07:40:37:elinks:INFO: Disabling clock on downlink 2
07:40:37:elinks:INFO: Disabling clock on downlink 3
07:40:37:elinks:INFO: Disabling clock on downlink 4
07:40:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
07:40:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:37:elinks:INFO: Disabling clock on downlink 0
07:40:37:elinks:INFO: Disabling clock on downlink 1
07:40:37:elinks:INFO: Disabling clock on downlink 2
07:40:37:elinks:INFO: Disabling clock on downlink 3
07:40:37:elinks:INFO: Disabling clock on downlink 4
07:40:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:37:elinks:INFO: Disabling clock on downlink 0
07:40:37:elinks:INFO: Disabling clock on downlink 1
07:40:37:elinks:INFO: Disabling clock on downlink 2
07:40:37:elinks:INFO: Disabling clock on downlink 3
07:40:37:elinks:INFO: Disabling clock on downlink 4
07:40:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
07:40:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
07:40:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
07:40:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
07:40:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
07:40:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
07:40:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
07:40:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
07:40:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:38:elinks:INFO: Disabling clock on downlink 0
07:40:38:elinks:INFO: Disabling clock on downlink 1
07:40:38:elinks:INFO: Disabling clock on downlink 2
07:40:38:elinks:INFO: Disabling clock on downlink 3
07:40:38:elinks:INFO: Disabling clock on downlink 4
07:40:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
07:40:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:38:elinks:INFO: Disabling clock on downlink 0
07:40:38:elinks:INFO: Disabling clock on downlink 1
07:40:38:elinks:INFO: Disabling clock on downlink 2
07:40:38:elinks:INFO: Disabling clock on downlink 3
07:40:38:elinks:INFO: Disabling clock on downlink 4
07:40:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
07:40:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:38:setup_element:INFO: Scanning clock phase
07:40:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:38:setup_element:INFO: Clock phase scan results for group 0, downlink 2
07:40:38:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
07:40:38:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
07:40:38:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXX____
Clock Delay: 32
07:40:38:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXX____
Clock Delay: 32
07:40:38:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:40:38:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:40:38:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
07:40:38:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
07:40:38:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
07:40:38:setup_element:INFO: Scanning data phases
07:40:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:43:setup_element:INFO: Data phase scan results for group 0, downlink 2
07:40:43:setup_element:INFO: Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
07:40:43:setup_element:INFO: Eye window for uplink 25: __________XXXXXX________________________
Data delay found: 32
07:40:43:setup_element:INFO: Eye window for uplink 26: ________XXXXXXX_________________________
Data delay found: 31
07:40:43:setup_element:INFO: Eye window for uplink 27: __________XXXXXXX_______________________
Data delay found: 33
07:40:43:setup_element:INFO: Eye window for uplink 28: _______________XXXXXX___________________
Data delay found: 37
07:40:43:setup_element:INFO: Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
07:40:43:setup_element:INFO: Eye window for uplink 30: _________________XXXXXXX________________
Data delay found: 0
07:40:43:setup_element:INFO: Eye window for uplink 31: ________________XXXXXX__________________
Data delay found: 38
07:40:43:setup_element:INFO: Setting the data phase to 31 for uplink 24
07:40:43:setup_element:INFO: Setting the data phase to 32 for uplink 25
07:40:43:setup_element:INFO: Setting the data phase to 31 for uplink 26
07:40:43:setup_element:INFO: Setting the data phase to 33 for uplink 27
07:40:43:setup_element:INFO: Setting the data phase to 37 for uplink 28
07:40:43:setup_element:INFO: Setting the data phase to 37 for uplink 29
07:40:43:setup_element:INFO: Setting the data phase to 0 for uplink 30
07:40:43:setup_element:INFO: Setting the data phase to 38 for uplink 31
07:40:43:setup_element:INFO: Beginning SMX ASICs map scan
07:40:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
07:40:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
07:40:43:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
07:40:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
07:40:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
07:40:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
07:40:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
07:40:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
07:40:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
07:40:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
07:40:45:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
07:40:46:setup_element:INFO: Performing Elink synchronization
07:40:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:46:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
07:40:46:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
07:40:46:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
07:40:46:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
07:40:46:febtest:INFO: Init all SMX (CSA): 30
07:40:55:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:40:55:febtest:INFO: 30-01 | XA-000-09-004-019-006-008-15 | 44.1 | 1141.9
07:40:55:febtest:INFO: 28-03 | XA-000-09-004-019-015-008-14 | 34.6 | 1165.6
07:40:56:febtest:INFO: 26-05 | XA-000-09-004-019-015-006-14 | 40.9 | 1135.9
07:40:56:febtest:INFO: 24-07 | XA-000-09-004-019-009-008-11 | 37.7 | 1171.5
07:40:57:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
07:40:59:ST3_smx:INFO: chip: 30-1 40.898880 C 1153.732915 mV
07:40:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:59:ST3_smx:INFO: Electrons
07:40:59:ST3_smx:INFO: # loops 0
07:41:00:ST3_smx:INFO: # loops 1
07:41:02:ST3_smx:INFO: # loops 2
07:41:03:ST3_smx:INFO: Total # of broken channels: 0
07:41:03:ST3_smx:INFO: List of broken channels: []
07:41:03:ST3_smx:INFO: Total # of broken channels: 0
07:41:03:ST3_smx:INFO: List of broken channels: []
07:41:05:ST3_smx:INFO: chip: 28-3 34.556970 C 1177.390875 mV
07:41:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:05:ST3_smx:INFO: Electrons
07:41:05:ST3_smx:INFO: # loops 0
07:41:07:ST3_smx:INFO: # loops 1
07:41:08:ST3_smx:INFO: # loops 2
07:41:10:ST3_smx:INFO: Total # of broken channels: 0
07:41:10:ST3_smx:INFO: List of broken channels: []
07:41:10:ST3_smx:INFO: Total # of broken channels: 0
07:41:10:ST3_smx:INFO: List of broken channels: []
07:41:11:ST3_smx:INFO: chip: 26-5 44.073563 C 1147.806000 mV
07:41:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:11:ST3_smx:INFO: Electrons
07:41:11:ST3_smx:INFO: # loops 0
07:41:13:ST3_smx:INFO: # loops 1
07:41:15:ST3_smx:INFO: # loops 2
07:41:16:ST3_smx:INFO: Total # of broken channels: 0
07:41:16:ST3_smx:INFO: List of broken channels: []
07:41:16:ST3_smx:INFO: Total # of broken channels: 0
07:41:16:ST3_smx:INFO: List of broken channels: []
07:41:18:ST3_smx:INFO: chip: 24-7 37.726682 C 1177.390875 mV
07:41:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:18:ST3_smx:INFO: Electrons
07:41:18:ST3_smx:INFO: # loops 0
07:41:19:ST3_smx:INFO: # loops 1
07:41:21:ST3_smx:INFO: # loops 2
07:41:23:ST3_smx:INFO: Total # of broken channels: 0
07:41:23:ST3_smx:INFO: List of broken channels: []
07:41:23:ST3_smx:INFO: Total # of broken channels: 0
07:41:23:ST3_smx:INFO: List of broken channels: []
07:41:23:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:41:23:febtest:INFO: 30-01 | XA-000-09-004-019-006-008-15 | 44.1 | 1171.5
07:41:24:febtest:INFO: 28-03 | XA-000-09-004-019-015-008-14 | 34.6 | 1201.0
07:41:24:febtest:INFO: 26-05 | XA-000-09-004-019-015-006-14 | 44.1 | 1165.6
07:41:24:febtest:INFO: 24-07 | XA-000-09-004-019-009-008-11 | 37.7 | 1201.0
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_11-07_40_35
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4170| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.451', '0.7645', '1.850', '1.0320']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0100', '1.850', '1.2900']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9936', '1.850', '0.2680']