DTL-STS tests database

FEB_4191 05.08.25 08:47:01

link: XA-000-09-004-024-009-010-05
...SMX_0.root
link: XA-000-09-004-024-015-010-00
...SMX_2.root
link: XA-000-09-004-024-012-010-14
...SMX_4.root
link: XA-000-09-004-024-012-011-14
...SMX_6.root
link: XA-000-09-004-024-006-010-01
...SMX_1.root
link: XA-000-09-004-024-006-009-01
...SMX_3.root
link: XA-000-09-004-024-003-008-10
...SMX_5.root
link: XA-000-09-004-024-018-010-11
...SMX_7.root
link: XA-000-09-004-024-018-010-11
...VddmCSAstatus.root
Info
            08:47:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:47:01:ST3_Shared:INFO:	                       FEB-Microcable                       
08:47:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:47:01:febtest:INFO:	Testing FEB with SN 4191
08:47:03:smx_tester:INFO:	Scanning setup
08:47:03:elinks:INFO:	Disabling clock on downlink 0
08:47:03:elinks:INFO:	Disabling clock on downlink 1
08:47:03:elinks:INFO:	Disabling clock on downlink 2
08:47:03:elinks:INFO:	Disabling clock on downlink 3
08:47:03:elinks:INFO:	Disabling clock on downlink 4
08:47:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
08:47:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:47:03:elinks:INFO:	Disabling clock on downlink 0
08:47:03:elinks:INFO:	Disabling clock on downlink 1
08:47:03:elinks:INFO:	Disabling clock on downlink 2
08:47:03:elinks:INFO:	Disabling clock on downlink 3
08:47:03:elinks:INFO:	Disabling clock on downlink 4
08:47:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:47:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:47:03:elinks:INFO:	Disabling clock on downlink 0
08:47:03:elinks:INFO:	Disabling clock on downlink 1
08:47:03:elinks:INFO:	Disabling clock on downlink 2
08:47:03:elinks:INFO:	Disabling clock on downlink 3
08:47:03:elinks:INFO:	Disabling clock on downlink 4
08:47:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
08:47:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
08:47:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:47:03:elinks:INFO:	Disabling clock on downlink 0
08:47:03:elinks:INFO:	Disabling clock on downlink 1
08:47:03:elinks:INFO:	Disabling clock on downlink 2
08:47:03:elinks:INFO:	Disabling clock on downlink 3
08:47:03:elinks:INFO:	Disabling clock on downlink 4
08:47:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
08:47:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:47:03:elinks:INFO:	Disabling clock on downlink 0
08:47:03:elinks:INFO:	Disabling clock on downlink 1
08:47:03:elinks:INFO:	Disabling clock on downlink 2
08:47:03:elinks:INFO:	Disabling clock on downlink 3
08:47:03:elinks:INFO:	Disabling clock on downlink 4
08:47:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
08:47:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:47:03:setup_element:INFO:	Scanning clock phase
08:47:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:47:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:47:04:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
08:47:04:setup_element:INFO:	Eye window for uplink 16: ________________________________________________________________________XXXX____
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 17: ________________________________________________________________________XXXX____
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 18: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 19: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 20: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 21: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 22: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 23: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 24: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 25: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:47:04:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:47:04:setup_element:INFO:	Eye window for uplink 30: _________________________________________________________________________XXXXX__
Clock Delay: 35
08:47:04:setup_element:INFO:	Eye window for uplink 31: _________________________________________________________________________XXXXX__
Clock Delay: 35
08:47:04:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
08:47:04:setup_element:INFO:	Scanning data phases
08:47:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:47:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:47:09:setup_element:INFO:	Data phase scan results for group 0, downlink 2
08:47:09:setup_element:INFO:	Eye window for uplink 16: ___________________________________XXXX_
Data delay found: 16
08:47:09:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXX__
Data delay found: 15
08:47:09:setup_element:INFO:	Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
08:47:09:setup_element:INFO:	Eye window for uplink 19: __________________________________XXXXXX
Data delay found: 16
08:47:09:setup_element:INFO:	Eye window for uplink 20: ___________________________________XXXX_
Data delay found: 16
08:47:09:setup_element:INFO:	Eye window for uplink 21: X___________________________________XXXX
Data delay found: 18
08:47:09:setup_element:INFO:	Eye window for uplink 22: __________________________________XXXXX_
Data delay found: 16
08:47:09:setup_element:INFO:	Eye window for uplink 23: _______________________________XXXXX____
Data delay found: 13
08:47:09:setup_element:INFO:	Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
08:47:09:setup_element:INFO:	Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
08:47:09:setup_element:INFO:	Eye window for uplink 26: _________XXXXXXX________________________
Data delay found: 32
08:47:09:setup_element:INFO:	Eye window for uplink 27: ___________XXXXXXX______________________
Data delay found: 34
08:47:09:setup_element:INFO:	Eye window for uplink 28: __________XXXXXX________________________
Data delay found: 32
08:47:09:setup_element:INFO:	Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
08:47:09:setup_element:INFO:	Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
08:47:09:setup_element:INFO:	Eye window for uplink 31: _______________XXXX_____________________
Data delay found: 36
08:47:09:setup_element:INFO:	Setting the data phase to 16 for uplink 16
08:47:09:setup_element:INFO:	Setting the data phase to 15 for uplink 17
08:47:09:setup_element:INFO:	Setting the data phase to 16 for uplink 18
08:47:09:setup_element:INFO:	Setting the data phase to 16 for uplink 19
08:47:09:setup_element:INFO:	Setting the data phase to 16 for uplink 20
08:47:09:setup_element:INFO:	Setting the data phase to 18 for uplink 21
08:47:09:setup_element:INFO:	Setting the data phase to 16 for uplink 22
08:47:09:setup_element:INFO:	Setting the data phase to 13 for uplink 23
08:47:09:setup_element:INFO:	Setting the data phase to 31 for uplink 24
08:47:09:setup_element:INFO:	Setting the data phase to 32 for uplink 25
08:47:09:setup_element:INFO:	Setting the data phase to 32 for uplink 26
08:47:09:setup_element:INFO:	Setting the data phase to 34 for uplink 27
08:47:09:setup_element:INFO:	Setting the data phase to 32 for uplink 28
08:47:09:setup_element:INFO:	Setting the data phase to 32 for uplink 29
08:47:09:setup_element:INFO:	Setting the data phase to 37 for uplink 30
08:47:09:setup_element:INFO:	Setting the data phase to 36 for uplink 31
08:47:09:setup_element:INFO:	Beginning SMX ASICs map scan
08:47:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:47:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:47:09:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:47:09:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:47:09:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:47:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:47:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:47:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:47:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:47:09:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:47:09:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:47:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:47:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:47:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:47:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:47:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:47:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:47:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:47:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:47:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:47:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:47:12:setup_element:INFO:	Performing Elink synchronization
08:47:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:47:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:47:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:47:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:47:12:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
08:47:12:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:47:13:febtest:INFO:	Init all SMX (CSA): 30
08:47:31:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:47:31:febtest:INFO:	23-00 | XA-000-09-004-024-009-010-05 |  31.4 | 1183.3
08:47:32:febtest:INFO:	30-01 | XA-000-09-004-024-006-010-01 |  47.3 | 1124.0
08:47:32:febtest:INFO:	21-02 | XA-000-09-004-024-015-010-00 |  31.4 | 1201.0
08:47:32:febtest:INFO:	28-03 | XA-000-09-004-024-006-009-01 |  44.1 | 1141.9
08:47:32:febtest:INFO:	19-04 | XA-000-09-004-024-012-010-14 |  40.9 | 1153.7
08:47:32:febtest:INFO:	26-05 | XA-000-09-004-024-003-008-10 |  37.7 | 1171.5
08:47:33:febtest:INFO:	17-06 | XA-000-09-004-024-012-011-14 |  37.7 | 1171.5
08:47:33:febtest:INFO:	24-07 | XA-000-09-004-024-018-010-11 |  40.9 | 1147.8
08:47:34:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:47:36:ST3_smx:INFO:	chip: 23-0 	 31.389742 C 	 1195.082160 mV
08:47:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:36:ST3_smx:INFO:		Electrons
08:47:36:ST3_smx:INFO:	# loops 0
08:47:38:ST3_smx:INFO:	# loops 1
08:47:40:ST3_smx:INFO:	# loops 2
08:47:42:ST3_smx:INFO:	Total # of broken channels: 0
08:47:42:ST3_smx:INFO:	List of broken channels: []
08:47:42:ST3_smx:INFO:	Total # of broken channels: 0
08:47:42:ST3_smx:INFO:	List of broken channels: []
08:47:43:ST3_smx:INFO:	chip: 30-1 	 47.250730 C 	 1135.937260 mV
08:47:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:43:ST3_smx:INFO:		Electrons
08:47:43:ST3_smx:INFO:	# loops 0
08:47:45:ST3_smx:INFO:	# loops 1
08:47:47:ST3_smx:INFO:	# loops 2
08:47:49:ST3_smx:INFO:	Total # of broken channels: 0
08:47:49:ST3_smx:INFO:	List of broken channels: []
08:47:49:ST3_smx:INFO:	Total # of broken channels: 0
08:47:49:ST3_smx:INFO:	List of broken channels: []
08:47:51:ST3_smx:INFO:	chip: 21-2 	 31.389742 C 	 1212.728715 mV
08:47:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:51:ST3_smx:INFO:		Electrons
08:47:51:ST3_smx:INFO:	# loops 0
08:47:52:ST3_smx:INFO:	# loops 1
08:47:54:ST3_smx:INFO:	# loops 2
08:47:56:ST3_smx:INFO:	Total # of broken channels: 0
08:47:56:ST3_smx:INFO:	List of broken channels: []
08:47:56:ST3_smx:INFO:	Total # of broken channels: 0
08:47:56:ST3_smx:INFO:	List of broken channels: []
08:47:58:ST3_smx:INFO:	chip: 28-3 	 44.073563 C 	 1153.732915 mV
08:47:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:47:58:ST3_smx:INFO:		Electrons
08:47:58:ST3_smx:INFO:	# loops 0
08:48:00:ST3_smx:INFO:	# loops 1
08:48:02:ST3_smx:INFO:	# loops 2
08:48:05:ST3_smx:INFO:	Total # of broken channels: 0
08:48:05:ST3_smx:INFO:	List of broken channels: []
08:48:05:ST3_smx:INFO:	Total # of broken channels: 0
08:48:05:ST3_smx:INFO:	List of broken channels: []
08:48:06:ST3_smx:INFO:	chip: 19-4 	 44.073563 C 	 1165.571835 mV
08:48:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:06:ST3_smx:INFO:		Electrons
08:48:06:ST3_smx:INFO:	# loops 0
08:48:08:ST3_smx:INFO:	# loops 1
08:48:11:ST3_smx:INFO:	# loops 2
08:48:13:ST3_smx:INFO:	Total # of broken channels: 0
08:48:13:ST3_smx:INFO:	List of broken channels: []
08:48:13:ST3_smx:INFO:	Total # of broken channels: 0
08:48:13:ST3_smx:INFO:	List of broken channels: []
08:48:15:ST3_smx:INFO:	chip: 26-5 	 37.726682 C 	 1183.292940 mV
08:48:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:15:ST3_smx:INFO:		Electrons
08:48:15:ST3_smx:INFO:	# loops 0
08:48:16:ST3_smx:INFO:	# loops 1
08:48:18:ST3_smx:INFO:	# loops 2
08:48:20:ST3_smx:INFO:	Total # of broken channels: 0
08:48:20:ST3_smx:INFO:	List of broken channels: []
08:48:20:ST3_smx:INFO:	Total # of broken channels: 0
08:48:20:ST3_smx:INFO:	List of broken channels: []
08:48:22:ST3_smx:INFO:	chip: 17-6 	 40.898880 C 	 1183.292940 mV
08:48:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:22:ST3_smx:INFO:		Electrons
08:48:22:ST3_smx:INFO:	# loops 0
08:48:24:ST3_smx:INFO:	# loops 1
08:48:26:ST3_smx:INFO:	# loops 2
08:48:28:ST3_smx:INFO:	Total # of broken channels: 0
08:48:28:ST3_smx:INFO:	List of broken channels: []
08:48:28:ST3_smx:INFO:	Total # of broken channels: 0
08:48:28:ST3_smx:INFO:	List of broken channels: []
08:48:30:ST3_smx:INFO:	chip: 24-7 	 44.073563 C 	 1159.654860 mV
08:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:48:30:ST3_smx:INFO:		Electrons
08:48:30:ST3_smx:INFO:	# loops 0
08:48:32:ST3_smx:INFO:	# loops 1
08:48:34:ST3_smx:INFO:	# loops 2
08:48:36:ST3_smx:INFO:	Total # of broken channels: 0
08:48:36:ST3_smx:INFO:	List of broken channels: []
08:48:36:ST3_smx:INFO:	Total # of broken channels: 0
08:48:36:ST3_smx:INFO:	List of broken channels: []
08:48:36:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:48:37:febtest:INFO:	23-00 | XA-000-09-004-024-009-010-05 |  34.6 | 1230.3
08:48:37:febtest:INFO:	30-01 | XA-000-09-004-024-006-010-01 |  50.4 | 1159.7
08:48:37:febtest:INFO:	21-02 | XA-000-09-004-024-015-010-00 |  31.4 | 1242.0
08:48:37:febtest:INFO:	28-03 | XA-000-09-004-024-006-009-01 |  47.3 | 1177.4
08:48:37:febtest:INFO:	19-04 | XA-000-09-004-024-012-010-14 |  44.1 | 1189.2
08:48:38:febtest:INFO:	26-05 | XA-000-09-004-024-003-008-10 |  40.9 | 1206.9
08:48:38:febtest:INFO:	17-06 | XA-000-09-004-024-012-011-14 |  40.9 | 1201.0
08:48:38:febtest:INFO:	24-07 | XA-000-09-004-024-018-010-11 |  47.3 | 1183.3
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_08_05-08_47_01
OPERATOR  : Alois Alzheimer
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4191| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5250', '1.849', '2.4780']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0060', '1.850', '2.4970']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9900', '1.850', '0.5260']
Comment