FEB_4192 01.08.25 11:01:17
Info
11:01:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:01:17:ST3_Shared:INFO: FEB-Microcable
11:01:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:01:17:febtest:INFO: Testing FEB with SN 4192
11:01:19:smx_tester:INFO: Scanning setup
11:01:19:elinks:INFO: Disabling clock on downlink 0
11:01:19:elinks:INFO: Disabling clock on downlink 1
11:01:19:elinks:INFO: Disabling clock on downlink 2
11:01:19:elinks:INFO: Disabling clock on downlink 3
11:01:19:elinks:INFO: Disabling clock on downlink 4
11:01:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:01:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:01:19:elinks:INFO: Disabling clock on downlink 0
11:01:19:elinks:INFO: Disabling clock on downlink 1
11:01:19:elinks:INFO: Disabling clock on downlink 2
11:01:19:elinks:INFO: Disabling clock on downlink 3
11:01:19:elinks:INFO: Disabling clock on downlink 4
11:01:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:01:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:01:19:elinks:INFO: Disabling clock on downlink 0
11:01:19:elinks:INFO: Disabling clock on downlink 1
11:01:19:elinks:INFO: Disabling clock on downlink 2
11:01:19:elinks:INFO: Disabling clock on downlink 3
11:01:19:elinks:INFO: Disabling clock on downlink 4
11:01:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:01:19:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:01:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:01:19:elinks:INFO: Disabling clock on downlink 0
11:01:19:elinks:INFO: Disabling clock on downlink 1
11:01:19:elinks:INFO: Disabling clock on downlink 2
11:01:19:elinks:INFO: Disabling clock on downlink 3
11:01:19:elinks:INFO: Disabling clock on downlink 4
11:01:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:01:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:01:19:elinks:INFO: Disabling clock on downlink 0
11:01:19:elinks:INFO: Disabling clock on downlink 1
11:01:19:elinks:INFO: Disabling clock on downlink 2
11:01:19:elinks:INFO: Disabling clock on downlink 3
11:01:19:elinks:INFO: Disabling clock on downlink 4
11:01:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:01:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:01:19:setup_element:INFO: Scanning clock phase
11:01:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:01:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:01:20:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:01:20:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:01:20:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:01:20:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXX______
Clock Delay: 31
11:01:20:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXX______
Clock Delay: 31
11:01:20:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXX______
Clock Delay: 31
11:01:20:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXX______
Clock Delay: 31
11:01:20:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:01:20:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:01:20:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
11:01:20:setup_element:INFO: Scanning data phases
11:01:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:01:20:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:01:25:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:01:25:setup_element:INFO: Eye window for uplink 24: _________XXXXXX_________________________
Data delay found: 31
11:01:25:setup_element:INFO: Eye window for uplink 25: ___________XXXXX________________________
Data delay found: 33
11:01:25:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________
Data delay found: 27
11:01:25:setup_element:INFO: Eye window for uplink 27: ______XXXXXXX___________________________
Data delay found: 29
11:01:25:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
11:01:25:setup_element:INFO: Eye window for uplink 29: __________XXXX__________________________
Data delay found: 31
11:01:25:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
11:01:25:setup_element:INFO: Eye window for uplink 31: ______________XXXXX_____________________
Data delay found: 36
11:01:25:setup_element:INFO: Setting the data phase to 31 for uplink 24
11:01:25:setup_element:INFO: Setting the data phase to 33 for uplink 25
11:01:25:setup_element:INFO: Setting the data phase to 27 for uplink 26
11:01:25:setup_element:INFO: Setting the data phase to 29 for uplink 27
11:01:25:setup_element:INFO: Setting the data phase to 32 for uplink 28
11:01:25:setup_element:INFO: Setting the data phase to 31 for uplink 29
11:01:25:setup_element:INFO: Setting the data phase to 37 for uplink 30
11:01:25:setup_element:INFO: Setting the data phase to 36 for uplink 31
11:01:25:setup_element:INFO: Beginning SMX ASICs map scan
11:01:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:01:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:01:25:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:01:25:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:01:25:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
11:01:25:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:01:25:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:01:25:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:01:25:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:01:26:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:01:26:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:01:26:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:01:26:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:01:27:setup_element:INFO: Performing Elink synchronization
11:01:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:01:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:01:27:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:01:27:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:01:27:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:01:27:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:01:28:febtest:INFO: Init all SMX (CSA): 30
11:01:37:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:01:37:febtest:INFO: 30-01 | XA-000-09-004-024-003-011-10 | 25.1 | 1189.2
11:01:37:febtest:INFO: 28-03 | XA-000-09-004-024-015-012-00 | 28.2 | 1189.2
11:01:37:febtest:INFO: 26-05 | XA-000-09-004-024-012-012-14 | 40.9 | 1147.8
11:01:38:febtest:INFO: 24-07 | XA-000-09-004-024-009-002-05 | 47.3 | 1124.0
11:01:39:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:01:41:ST3_smx:INFO: chip: 30-1 25.062742 C 1200.969315 mV
11:01:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:41:ST3_smx:INFO: Electrons
11:01:41:ST3_smx:INFO: # loops 0
11:01:43:ST3_smx:INFO: # loops 1
11:01:45:ST3_smx:INFO: # loops 2
11:01:47:ST3_smx:INFO: Total # of broken channels: 0
11:01:47:ST3_smx:INFO: List of broken channels: []
11:01:47:ST3_smx:INFO: Total # of broken channels: 0
11:01:47:ST3_smx:INFO: List of broken channels: []
11:01:48:ST3_smx:INFO: chip: 28-3 28.225000 C 1195.082160 mV
11:01:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:48:ST3_smx:INFO: Electrons
11:01:48:ST3_smx:INFO: # loops 0
11:01:50:ST3_smx:INFO: # loops 1
11:01:52:ST3_smx:INFO: # loops 2
11:01:54:ST3_smx:INFO: Total # of broken channels: 0
11:01:54:ST3_smx:INFO: List of broken channels: []
11:01:54:ST3_smx:INFO: Total # of broken channels: 0
11:01:54:ST3_smx:INFO: List of broken channels: []
11:01:56:ST3_smx:INFO: chip: 26-5 40.898880 C 1159.654860 mV
11:01:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:01:56:ST3_smx:INFO: Electrons
11:01:56:ST3_smx:INFO: # loops 0
11:01:58:ST3_smx:INFO: # loops 1
11:02:00:ST3_smx:INFO: # loops 2
11:02:02:ST3_smx:INFO: Total # of broken channels: 0
11:02:02:ST3_smx:INFO: List of broken channels: []
11:02:02:ST3_smx:INFO: Total # of broken channels: 0
11:02:02:ST3_smx:INFO: List of broken channels: []
11:02:04:ST3_smx:INFO: chip: 24-7 47.250730 C 1129.995435 mV
11:02:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:02:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:02:04:ST3_smx:INFO: Electrons
11:02:04:ST3_smx:INFO: # loops 0
11:02:06:ST3_smx:INFO: # loops 1
11:02:08:ST3_smx:INFO: # loops 2
11:02:10:ST3_smx:INFO: Total # of broken channels: 0
11:02:10:ST3_smx:INFO: List of broken channels: []
11:02:10:ST3_smx:INFO: Total # of broken channels: 0
11:02:10:ST3_smx:INFO: List of broken channels: []
11:02:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:02:10:febtest:INFO: 30-01 | XA-000-09-004-024-003-011-10 | 25.1 | 1224.5
11:02:10:febtest:INFO: 28-03 | XA-000-09-004-024-015-012-00 | 28.2 | 1218.6
11:02:11:febtest:INFO: 26-05 | XA-000-09-004-024-012-012-14 | 40.9 | 1183.3
11:02:11:febtest:INFO: 24-07 | XA-000-09-004-024-009-002-05 | 50.4 | 1153.7
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_08_01-11_01_17
OPERATOR : Alois Alzheimer
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4192| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7184', '1.850', '1.0900']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0060', '1.850', '1.2510']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9970', '1.850', '0.2625']