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FEB_4196 10.07.25 07:40:50
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07:40:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:40:50:ST3_Shared:INFO: FEB-Microcable
07:40:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:40:50:febtest:INFO: Testing FEB with SN 4196
07:40:51:smx_tester:INFO: Scanning setup
07:40:51:elinks:INFO: Disabling clock on downlink 0
07:40:51:elinks:INFO: Disabling clock on downlink 1
07:40:51:elinks:INFO: Disabling clock on downlink 2
07:40:51:elinks:INFO: Disabling clock on downlink 3
07:40:51:elinks:INFO: Disabling clock on downlink 4
07:40:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
07:40:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:51:elinks:INFO: Disabling clock on downlink 0
07:40:51:elinks:INFO: Disabling clock on downlink 1
07:40:51:elinks:INFO: Disabling clock on downlink 2
07:40:51:elinks:INFO: Disabling clock on downlink 3
07:40:51:elinks:INFO: Disabling clock on downlink 4
07:40:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:51:elinks:INFO: Disabling clock on downlink 0
07:40:51:elinks:INFO: Disabling clock on downlink 1
07:40:51:elinks:INFO: Disabling clock on downlink 2
07:40:51:elinks:INFO: Disabling clock on downlink 3
07:40:51:elinks:INFO: Disabling clock on downlink 4
07:40:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
07:40:52:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
07:40:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:52:elinks:INFO: Disabling clock on downlink 0
07:40:52:elinks:INFO: Disabling clock on downlink 1
07:40:52:elinks:INFO: Disabling clock on downlink 2
07:40:52:elinks:INFO: Disabling clock on downlink 3
07:40:52:elinks:INFO: Disabling clock on downlink 4
07:40:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
07:40:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:52:elinks:INFO: Disabling clock on downlink 0
07:40:52:elinks:INFO: Disabling clock on downlink 1
07:40:52:elinks:INFO: Disabling clock on downlink 2
07:40:52:elinks:INFO: Disabling clock on downlink 3
07:40:52:elinks:INFO: Disabling clock on downlink 4
07:40:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
07:40:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:52:setup_element:INFO: Scanning clock phase
07:40:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:52:setup_element:INFO: Clock phase scan results for group 0, downlink 2
07:40:52:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
07:40:52:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
07:40:52:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:40:52:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXXX__
Clock Delay: 34
07:40:52:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXX_
Clock Delay: 35
07:40:52:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXX_
Clock Delay: 35
07:40:52:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
07:40:52:setup_element:INFO: Scanning data phases
07:40:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:57:setup_element:INFO: Data phase scan results for group 0, downlink 2
07:40:57:setup_element:INFO: Eye window for uplink 16: XXX__________________________________XXX
Data delay found: 19
07:40:57:setup_element:INFO: Eye window for uplink 17: X___________________________________XXXX
Data delay found: 18
07:40:57:setup_element:INFO: Eye window for uplink 18: X___________________________________XXXX
Data delay found: 18
07:40:57:setup_element:INFO: Eye window for uplink 19: X___________________________________XXXX
Data delay found: 18
07:40:57:setup_element:INFO: Eye window for uplink 20: XXXXX__________________________________X
Data delay found: 21
07:40:57:setup_element:INFO: Eye window for uplink 21: _XXXXX__________________________________
Data delay found: 23
07:40:57:setup_element:INFO: Eye window for uplink 22: XXX__________________________________XXX
Data delay found: 19
07:40:57:setup_element:INFO: Eye window for uplink 23: __________________________________XXXXX_
Data delay found: 16
07:40:57:setup_element:INFO: Eye window for uplink 24: ________XXXXXX__________________________
Data delay found: 30
07:40:57:setup_element:INFO: Eye window for uplink 25: __________XXXXXX________________________
Data delay found: 32
07:40:57:setup_element:INFO: Eye window for uplink 26: ________XXXXXX__________________________
Data delay found: 30
07:40:57:setup_element:INFO: Eye window for uplink 27: _________XXXXXXX________________________
Data delay found: 32
07:40:57:setup_element:INFO: Eye window for uplink 28: _______________XXXXXX___________________
Data delay found: 37
07:40:57:setup_element:INFO: Eye window for uplink 29: _______________XXXXX____________________
Data delay found: 37
07:40:57:setup_element:INFO: Eye window for uplink 30: __________________XXXXXXX_______________
Data delay found: 1
07:40:57:setup_element:INFO: Eye window for uplink 31: _________________XXXXXX_________________
Data delay found: 39
07:40:57:setup_element:INFO: Setting the data phase to 19 for uplink 16
07:40:57:setup_element:INFO: Setting the data phase to 18 for uplink 17
07:40:57:setup_element:INFO: Setting the data phase to 18 for uplink 18
07:40:57:setup_element:INFO: Setting the data phase to 18 for uplink 19
07:40:57:setup_element:INFO: Setting the data phase to 21 for uplink 20
07:40:57:setup_element:INFO: Setting the data phase to 23 for uplink 21
07:40:57:setup_element:INFO: Setting the data phase to 19 for uplink 22
07:40:57:setup_element:INFO: Setting the data phase to 16 for uplink 23
07:40:57:setup_element:INFO: Setting the data phase to 30 for uplink 24
07:40:57:setup_element:INFO: Setting the data phase to 32 for uplink 25
07:40:58:setup_element:INFO: Setting the data phase to 30 for uplink 26
07:40:58:setup_element:INFO: Setting the data phase to 32 for uplink 27
07:40:58:setup_element:INFO: Setting the data phase to 37 for uplink 28
07:40:58:setup_element:INFO: Setting the data phase to 37 for uplink 29
07:40:58:setup_element:INFO: Setting the data phase to 1 for uplink 30
07:40:58:setup_element:INFO: Setting the data phase to 39 for uplink 31
07:40:58:setup_element:INFO: Beginning SMX ASICs map scan
07:40:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:40:58:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
07:40:58:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
07:40:58:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
07:40:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
07:40:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
07:40:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
07:40:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
07:40:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
07:40:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
07:40:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
07:40:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
07:40:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
07:40:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
07:40:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
07:40:59:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
07:40:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
07:40:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
07:40:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
07:40:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
07:41:00:setup_element:INFO: Performing Elink synchronization
07:41:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:41:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:41:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
07:41:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
07:41:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
07:41:00:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
07:41:01:febtest:INFO: Init all SMX (CSA): 30
07:41:15:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:41:15:febtest:INFO: 23-00 | XA-000-09-004-019-018-012-05 | 25.1 | 1177.4
07:41:15:febtest:INFO: 30-01 | XA-000-09-004-019-009-013-11 | 37.7 | 1153.7
07:41:15:febtest:INFO: 21-02 | XA-000-09-004-019-018-013-05 | 40.9 | 1130.0
07:41:15:febtest:INFO: 28-03 | XA-000-09-004-019-012-013-00 | 34.6 | 1159.7
07:41:16:febtest:INFO: 19-04 | XA-000-09-004-019-012-024-07 | 34.6 | 1159.7
07:41:16:febtest:INFO: 26-05 | XA-000-09-004-019-015-012-14 | 37.7 | 1153.7
07:41:16:febtest:INFO: 17-06 | XA-000-09-004-019-015-024-09 | 21.9 | 1189.2
07:41:16:febtest:INFO: 24-07 | XA-000-09-004-019-015-013-14 | 44.1 | 1130.0
07:41:17:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
07:41:19:ST3_smx:INFO: chip: 23-0 28.225000 C 1189.190035 mV
07:41:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:19:ST3_smx:INFO: Electrons
07:41:19:ST3_smx:INFO: # loops 0
07:41:21:ST3_smx:INFO: # loops 1
07:41:22:ST3_smx:INFO: # loops 2
07:41:24:ST3_smx:INFO: Total # of broken channels: 0
07:41:24:ST3_smx:INFO: List of broken channels: []
07:41:24:ST3_smx:INFO: Total # of broken channels: 0
07:41:24:ST3_smx:INFO: List of broken channels: []
07:41:26:ST3_smx:INFO: chip: 30-1 37.726682 C 1165.571835 mV
07:41:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:26:ST3_smx:INFO: Electrons
07:41:26:ST3_smx:INFO: # loops 0
07:41:28:ST3_smx:INFO: # loops 1
07:41:29:ST3_smx:INFO: # loops 2
07:41:31:ST3_smx:INFO: Total # of broken channels: 0
07:41:31:ST3_smx:INFO: List of broken channels: []
07:41:31:ST3_smx:INFO: Total # of broken channels: 0
07:41:31:ST3_smx:INFO: List of broken channels: []
07:41:33:ST3_smx:INFO: chip: 21-2 40.898880 C 1141.874115 mV
07:41:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:33:ST3_smx:INFO: Electrons
07:41:33:ST3_smx:INFO: # loops 0
07:41:35:ST3_smx:INFO: # loops 1
07:41:36:ST3_smx:INFO: # loops 2
07:41:38:ST3_smx:INFO: Total # of broken channels: 0
07:41:38:ST3_smx:INFO: List of broken channels: []
07:41:38:ST3_smx:INFO: Total # of broken channels: 1
07:41:38:ST3_smx:INFO: List of broken channels: [31]
07:41:39:ST3_smx:INFO: chip: 28-3 37.726682 C 1177.390875 mV
07:41:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:39:ST3_smx:INFO: Electrons
07:41:39:ST3_smx:INFO: # loops 0
07:41:41:ST3_smx:INFO: # loops 1
07:41:42:ST3_smx:INFO: # loops 2
07:41:44:ST3_smx:INFO: Total # of broken channels: 0
07:41:44:ST3_smx:INFO: List of broken channels: []
07:41:44:ST3_smx:INFO: Total # of broken channels: 1
07:41:44:ST3_smx:INFO: List of broken channels: [107]
07:41:46:ST3_smx:INFO: chip: 19-4 34.556970 C 1171.483840 mV
07:41:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:46:ST3_smx:INFO: Electrons
07:41:46:ST3_smx:INFO: # loops 0
07:41:47:ST3_smx:INFO: # loops 1
07:41:49:ST3_smx:INFO: # loops 2
07:41:50:ST3_smx:INFO: Total # of broken channels: 0
07:41:50:ST3_smx:INFO: List of broken channels: []
07:41:50:ST3_smx:INFO: Total # of broken channels: 0
07:41:50:ST3_smx:INFO: List of broken channels: []
07:41:52:ST3_smx:INFO: chip: 26-5 40.898880 C 1165.571835 mV
07:41:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:52:ST3_smx:INFO: Electrons
07:41:52:ST3_smx:INFO: # loops 0
07:41:54:ST3_smx:INFO: # loops 1
07:41:55:ST3_smx:INFO: # loops 2
07:41:57:ST3_smx:INFO: Total # of broken channels: 0
07:41:57:ST3_smx:INFO: List of broken channels: []
07:41:57:ST3_smx:INFO: Total # of broken channels: 0
07:41:57:ST3_smx:INFO: List of broken channels: []
07:41:58:ST3_smx:INFO: chip: 17-6 25.062742 C 1200.969315 mV
07:41:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:58:ST3_smx:INFO: Electrons
07:41:58:ST3_smx:INFO: # loops 0
07:42:00:ST3_smx:INFO: # loops 1
07:42:02:ST3_smx:INFO: # loops 2
07:42:03:ST3_smx:INFO: Total # of broken channels: 0
07:42:03:ST3_smx:INFO: List of broken channels: []
07:42:03:ST3_smx:INFO: Total # of broken channels: 0
07:42:03:ST3_smx:INFO: List of broken channels: []
07:42:05:ST3_smx:INFO: chip: 24-7 47.250730 C 1141.874115 mV
07:42:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:42:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:42:05:ST3_smx:INFO: Electrons
07:42:05:ST3_smx:INFO: # loops 0
07:42:07:ST3_smx:INFO: # loops 1
07:42:08:ST3_smx:INFO: # loops 2
07:42:10:ST3_smx:INFO: Total # of broken channels: 0
07:42:10:ST3_smx:INFO: List of broken channels: []
07:42:10:ST3_smx:INFO: Total # of broken channels: 0
07:42:10:ST3_smx:INFO: List of broken channels: []
07:42:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:42:10:febtest:INFO: 23-00 | XA-000-09-004-019-018-012-05 | 28.2 | 1218.6
07:42:11:febtest:INFO: 30-01 | XA-000-09-004-019-009-013-11 | 40.9 | 1189.2
07:42:11:febtest:INFO: 21-02 | XA-000-09-004-019-018-013-05 | 44.1 | 1165.6
07:42:11:febtest:INFO: 28-03 | XA-000-09-004-019-012-013-00 | 37.7 | 1195.1
07:42:11:febtest:INFO: 19-04 | XA-000-09-004-019-012-024-07 | 34.6 | 1195.1
07:42:12:febtest:INFO: 26-05 | XA-000-09-004-019-015-012-14 | 40.9 | 1195.1
07:42:12:febtest:INFO: 17-06 | XA-000-09-004-019-015-024-09 | 25.1 | 1224.5
07:42:12:febtest:INFO: 24-07 | XA-000-09-004-019-015-013-14 | 47.3 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_10-07_40_50
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4196| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5410', '1.846', '2.2570']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9990', '1.850', '2.6070']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9640', '1.850', '0.5226']