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FEB_4198 07.07.25 11:03:37
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11:03:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:03:37:ST3_Shared:INFO: FEB-Microcable
11:03:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:03:37:febtest:INFO: Testing FEB with SN 4198
11:03:39:smx_tester:INFO: Scanning setup
11:03:39:elinks:INFO: Disabling clock on downlink 0
11:03:39:elinks:INFO: Disabling clock on downlink 1
11:03:39:elinks:INFO: Disabling clock on downlink 2
11:03:39:elinks:INFO: Disabling clock on downlink 3
11:03:39:elinks:INFO: Disabling clock on downlink 4
11:03:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:03:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:03:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:03:39:elinks:INFO: Disabling clock on downlink 0
11:03:39:elinks:INFO: Disabling clock on downlink 1
11:03:39:elinks:INFO: Disabling clock on downlink 2
11:03:39:elinks:INFO: Disabling clock on downlink 3
11:03:39:elinks:INFO: Disabling clock on downlink 4
11:03:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:03:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:03:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:03:39:elinks:INFO: Disabling clock on downlink 0
11:03:39:elinks:INFO: Disabling clock on downlink 1
11:03:39:elinks:INFO: Disabling clock on downlink 2
11:03:39:elinks:INFO: Disabling clock on downlink 3
11:03:39:elinks:INFO: Disabling clock on downlink 4
11:03:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:03:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:03:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:03:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:03:39:elinks:INFO: Disabling clock on downlink 0
11:03:39:elinks:INFO: Disabling clock on downlink 1
11:03:39:elinks:INFO: Disabling clock on downlink 2
11:03:39:elinks:INFO: Disabling clock on downlink 3
11:03:39:elinks:INFO: Disabling clock on downlink 4
11:03:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:03:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:03:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:03:39:elinks:INFO: Disabling clock on downlink 0
11:03:39:elinks:INFO: Disabling clock on downlink 1
11:03:39:elinks:INFO: Disabling clock on downlink 2
11:03:39:elinks:INFO: Disabling clock on downlink 3
11:03:39:elinks:INFO: Disabling clock on downlink 4
11:03:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:03:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:03:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:03:40:setup_element:INFO: Scanning clock phase
11:03:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:03:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:40:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:03:40:setup_element:INFO: Eye window for uplink 24: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:03:40:setup_element:INFO: Eye window for uplink 25: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:03:40:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:03:40:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
11:03:40:setup_element:INFO: Scanning data phases
11:03:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:03:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:45:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:03:45:setup_element:INFO: Eye window for uplink 24: ________XXXXX___________________________
Data delay found: 30
11:03:45:setup_element:INFO: Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
11:03:45:setup_element:INFO: Eye window for uplink 26: ___________XXXXXXX______________________
Data delay found: 34
11:03:45:setup_element:INFO: Eye window for uplink 27: _____________XXXXXXX____________________
Data delay found: 36
11:03:45:setup_element:INFO: Eye window for uplink 28: _________________XXXXXX_________________
Data delay found: 39
11:03:45:setup_element:INFO: Eye window for uplink 29: _________________XXXXX__________________
Data delay found: 39
11:03:45:setup_element:INFO: Eye window for uplink 30: __________________XXXXXX________________
Data delay found: 0
11:03:45:setup_element:INFO: Eye window for uplink 31: _________________XXXXX__________________
Data delay found: 39
11:03:45:setup_element:INFO: Setting the data phase to 30 for uplink 24
11:03:45:setup_element:INFO: Setting the data phase to 32 for uplink 25
11:03:45:setup_element:INFO: Setting the data phase to 34 for uplink 26
11:03:45:setup_element:INFO: Setting the data phase to 36 for uplink 27
11:03:45:setup_element:INFO: Setting the data phase to 39 for uplink 28
11:03:45:setup_element:INFO: Setting the data phase to 39 for uplink 29
11:03:45:setup_element:INFO: Setting the data phase to 0 for uplink 30
11:03:45:setup_element:INFO: Setting the data phase to 39 for uplink 31
11:03:45:setup_element:INFO: Beginning SMX ASICs map scan
11:03:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:03:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:03:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:03:45:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
11:03:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:03:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:03:46:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:03:46:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:03:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:03:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:03:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:03:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:03:48:setup_element:INFO: Performing Elink synchronization
11:03:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:03:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:03:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:03:48:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:03:48:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:03:48:febtest:INFO: Init all SMX (CSA): 30
11:03:56:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:03:56:febtest:INFO: 30-01 | XA-000-09-004-019-003-021-03 | 31.4 | 1177.4
11:03:56:febtest:INFO: 28-03 | XA-000-09-004-019-006-022-08 | 40.9 | 1159.7
11:03:56:febtest:INFO: 26-05 | XA-000-09-004-019-012-022-07 | 44.1 | 1141.9
11:03:56:febtest:INFO: 24-07 | XA-000-09-004-019-012-021-07 | 37.7 | 1153.7
11:03:57:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:03:59:ST3_smx:INFO: chip: 30-1 31.389742 C 1189.190035 mV
11:03:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:59:ST3_smx:INFO: Electrons
11:03:59:ST3_smx:INFO: # loops 0
11:04:01:ST3_smx:INFO: # loops 1
11:04:03:ST3_smx:INFO: # loops 2
11:04:04:ST3_smx:INFO: Total # of broken channels: 0
11:04:04:ST3_smx:INFO: List of broken channels: []
11:04:04:ST3_smx:INFO: Total # of broken channels: 16
11:04:04:ST3_smx:INFO: List of broken channels: [26, 27, 28, 29, 30, 31, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50]
11:04:06:ST3_smx:INFO: chip: 28-3 40.898880 C 1171.483840 mV
11:04:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:06:ST3_smx:INFO: Electrons
11:04:06:ST3_smx:INFO: # loops 0
11:04:08:ST3_smx:INFO: # loops 1
11:04:10:ST3_smx:INFO: # loops 2
11:04:11:ST3_smx:INFO: Total # of broken channels: 0
11:04:11:ST3_smx:INFO: List of broken channels: []
11:04:11:ST3_smx:INFO: Total # of broken channels: 0
11:04:11:ST3_smx:INFO: List of broken channels: []
11:04:13:ST3_smx:INFO: chip: 26-5 44.073563 C 1147.806000 mV
11:04:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:13:ST3_smx:INFO: Electrons
11:04:13:ST3_smx:INFO: # loops 0
11:04:15:ST3_smx:INFO: # loops 1
11:04:16:ST3_smx:INFO: # loops 2
11:04:18:ST3_smx:INFO: Total # of broken channels: 0
11:04:18:ST3_smx:INFO: List of broken channels: []
11:04:18:ST3_smx:INFO: Total # of broken channels: 0
11:04:18:ST3_smx:INFO: List of broken channels: []
11:04:20:ST3_smx:INFO: chip: 24-7 40.898880 C 1159.654860 mV
11:04:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:04:20:ST3_smx:INFO: Electrons
11:04:20:ST3_smx:INFO: # loops 0
11:04:22:ST3_smx:INFO: # loops 1
11:04:23:ST3_smx:INFO: # loops 2
11:04:25:ST3_smx:INFO: Total # of broken channels: 0
11:04:25:ST3_smx:INFO: List of broken channels: []
11:04:25:ST3_smx:INFO: Total # of broken channels: 0
11:04:25:ST3_smx:INFO: List of broken channels: []
11:04:25:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:04:25:febtest:INFO: 30-01 | XA-000-09-004-019-003-021-03 | 34.6 | 1212.7
11:04:25:febtest:INFO: 28-03 | XA-000-09-004-019-006-022-08 | 40.9 | 1212.7
11:04:26:febtest:INFO: 26-05 | XA-000-09-004-019-012-022-07 | 47.3 | 1171.5
11:04:26:febtest:INFO: 24-07 | XA-000-09-004-019-012-021-07 | 44.1 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_07-11_03_37
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4198| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.2050', '1.846', '1.2240']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0120', '1.850', '1.2710']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9968', '1.850', '0.2683']