
FEB_4213 31.07.25 11:08:30
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11:08:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 11:08:30:ST3_Shared:INFO: FEB-Microcable 11:08:30:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 11:08:30:febtest:INFO: Testing FEB with SN 4213 11:08:32:smx_tester:INFO: Scanning setup 11:08:32:elinks:INFO: Disabling clock on downlink 0 11:08:32:elinks:INFO: Disabling clock on downlink 1 11:08:32:elinks:INFO: Disabling clock on downlink 2 11:08:32:elinks:INFO: Disabling clock on downlink 3 11:08:32:elinks:INFO: Disabling clock on downlink 4 11:08:32:setup_element:INFO: Checking SOS, encoding_mode: SOS 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 11:08:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 11:08:32:elinks:INFO: Disabling clock on downlink 0 11:08:32:elinks:INFO: Disabling clock on downlink 1 11:08:32:elinks:INFO: Disabling clock on downlink 2 11:08:32:elinks:INFO: Disabling clock on downlink 3 11:08:32:elinks:INFO: Disabling clock on downlink 4 11:08:32:setup_element:INFO: Checking SOS, encoding_mode: SOS 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 11:08:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 11:08:32:elinks:INFO: Disabling clock on downlink 0 11:08:32:elinks:INFO: Disabling clock on downlink 1 11:08:32:elinks:INFO: Disabling clock on downlink 2 11:08:32:elinks:INFO: Disabling clock on downlink 3 11:08:32:elinks:INFO: Disabling clock on downlink 4 11:08:32:setup_element:INFO: Checking SOS, encoding_mode: SOS 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30 11:08:32:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31 11:08:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 11:08:32:elinks:INFO: Disabling clock on downlink 0 11:08:32:elinks:INFO: Disabling clock on downlink 1 11:08:32:elinks:INFO: Disabling clock on downlink 2 11:08:32:elinks:INFO: Disabling clock on downlink 3 11:08:32:elinks:INFO: Disabling clock on downlink 4 11:08:32:setup_element:INFO: Checking SOS, encoding_mode: SOS 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 11:08:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 11:08:32:elinks:INFO: Disabling clock on downlink 0 11:08:32:elinks:INFO: Disabling clock on downlink 1 11:08:32:elinks:INFO: Disabling clock on downlink 2 11:08:32:elinks:INFO: Disabling clock on downlink 3 11:08:32:elinks:INFO: Disabling clock on downlink 4 11:08:32:setup_element:INFO: Checking SOS, encoding_mode: SOS 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 11:08:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 11:08:32:setup_element:INFO: Scanning clock phase 11:08:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 11:08:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 11:08:33:setup_element:INFO: Clock phase scan results for group 0, downlink 2 11:08:33:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXX____ Clock Delay: 33 11:08:33:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXX____ Clock Delay: 33 11:08:33:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXX____ Clock Delay: 32 11:08:33:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXX____ Clock Delay: 32 11:08:33:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 11:08:33:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 11:08:33:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXXXX___ Clock Delay: 33 11:08:33:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXXXX___ Clock Delay: 33 11:08:33:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2 11:08:33:setup_element:INFO: Scanning data phases 11:08:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 11:08:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 11:08:38:setup_element:INFO: Data phase scan results for group 0, downlink 2 11:08:38:setup_element:INFO: Eye window for uplink 24: ________XXXXXX__________________________ Data delay found: 30 11:08:38:setup_element:INFO: Eye window for uplink 25: __________XXXXXX________________________ Data delay found: 32 11:08:38:setup_element:INFO: Eye window for uplink 26: _________XXXXXX_________________________ Data delay found: 31 11:08:38:setup_element:INFO: Eye window for uplink 27: __________XXXXXXX_______________________ Data delay found: 33 11:08:38:setup_element:INFO: Eye window for uplink 28: ______________XXXXXXX___________________ Data delay found: 37 11:08:38:setup_element:INFO: Eye window for uplink 29: ______________XXXXXXX___________________ Data delay found: 37 11:08:38:setup_element:INFO: Eye window for uplink 30: ______________XXXXXXX___________________ Data delay found: 37 11:08:38:setup_element:INFO: Eye window for uplink 31: _____________XXXXX______________________ Data delay found: 35 11:08:38:setup_element:INFO: Setting the data phase to 30 for uplink 24 11:08:38:setup_element:INFO: Setting the data phase to 32 for uplink 25 11:08:38:setup_element:INFO: Setting the data phase to 31 for uplink 26 11:08:38:setup_element:INFO: Setting the data phase to 33 for uplink 27 11:08:38:setup_element:INFO: Setting the data phase to 37 for uplink 28 11:08:38:setup_element:INFO: Setting the data phase to 37 for uplink 29 11:08:38:setup_element:INFO: Setting the data phase to 37 for uplink 30 11:08:38:setup_element:INFO: Setting the data phase to 35 for uplink 31 11:08:38:setup_element:INFO: Beginning SMX ASICs map scan 11:08:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 11:08:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 11:08:38:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 11:08:38:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 11:08:38:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31] 11:08:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30 11:08:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31 11:08:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28 11:08:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29 11:08:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26 11:08:39:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27 11:08:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24 11:08:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25 11:08:40:setup_element:INFO: Performing Elink synchronization 11:08:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 11:08:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 11:08:40:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 11:08:40:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 11:08:40:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2 11:08:40:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31] |_________________________________________________________________________| _addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_ 1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)] 3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)] 5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)] 7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)] |_________________________________________________________________________| 11:08:41:febtest:INFO: Init all SMX (CSA): 30 11:08:48:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 11:08:48:febtest:INFO: 30-01 | XA-000-09-004-024-006-006-01 | 25.1 | 1183.3 11:08:48:febtest:INFO: 28-03 | XA-000-09-004-024-003-007-10 | 40.9 | 1153.7 11:08:48:febtest:INFO: 26-05 | XA-000-09-004-024-009-008-05 | 40.9 | 1141.9 11:08:49:febtest:INFO: 24-07 | XA-000-09-004-024-006-008-01 | 34.6 | 1171.5 11:08:50:febtest:INFO: Set all CSA to ZERO FEB type: B FEB_A: 0 FEB_B: 1 11:08:52:ST3_smx:INFO: chip: 30-1 25.062742 C 1195.082160 mV 11:08:52:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:08:52:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:08:52:ST3_smx:INFO: Electrons 11:08:52:ST3_smx:INFO: # loops 0 11:08:53:ST3_smx:INFO: # loops 1 11:08:55:ST3_smx:INFO: # loops 2 11:08:57:ST3_smx:INFO: Total # of broken channels: 0 11:08:57:ST3_smx:INFO: List of broken channels: [] 11:08:57:ST3_smx:INFO: Total # of broken channels: 0 11:08:57:ST3_smx:INFO: List of broken channels: [] 11:08:59:ST3_smx:INFO: chip: 28-3 40.898880 C 1165.571835 mV 11:08:59:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:08:59:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:08:59:ST3_smx:INFO: Electrons 11:08:59:ST3_smx:INFO: # loops 0 11:09:01:ST3_smx:INFO: # loops 1 11:09:02:ST3_smx:INFO: # loops 2 11:09:04:ST3_smx:INFO: Total # of broken channels: 0 11:09:04:ST3_smx:INFO: List of broken channels: [] 11:09:04:ST3_smx:INFO: Total # of broken channels: 0 11:09:04:ST3_smx:INFO: List of broken channels: [] 11:09:06:ST3_smx:INFO: chip: 26-5 40.898880 C 1153.732915 mV 11:09:06:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:09:06:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:09:06:ST3_smx:INFO: Electrons 11:09:06:ST3_smx:INFO: # loops 0 11:09:08:ST3_smx:INFO: # loops 1 11:09:09:ST3_smx:INFO: # loops 2 11:09:11:ST3_smx:INFO: Total # of broken channels: 0 11:09:11:ST3_smx:INFO: List of broken channels: [] 11:09:11:ST3_smx:INFO: Total # of broken channels: 0 11:09:11:ST3_smx:INFO: List of broken channels: [] 11:09:12:ST3_smx:INFO: chip: 24-7 34.556970 C 1183.292940 mV 11:09:12:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:09:12:ST3_discr_histo:WARNING: Not enough entries for fit!!! 11:09:12:ST3_smx:INFO: Electrons 11:09:12:ST3_smx:INFO: # loops 0 11:09:14:ST3_smx:INFO: # loops 1 11:09:16:ST3_smx:INFO: # loops 2 11:09:17:ST3_smx:INFO: Total # of broken channels: 0 11:09:17:ST3_smx:INFO: List of broken channels: [] 11:09:17:ST3_smx:INFO: Total # of broken channels: 0 11:09:17:ST3_smx:INFO: List of broken channels: [] 11:09:17:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 11:09:18:febtest:INFO: 30-01 | XA-000-09-004-024-006-006-01 | 25.1 | 1224.5 11:09:18:febtest:INFO: 28-03 | XA-000-09-004-024-003-007-10 | 40.9 | 1212.7 11:09:18:febtest:INFO: 26-05 | XA-000-09-004-024-009-008-05 | 40.9 | 1171.5 11:09:18:febtest:INFO: 24-07 | XA-000-09-004-024-006-008-01 | 37.7 | 1201.0 ############################################################ # S U M M A R Y # ############################################################ {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Microcable TEST_DATE : 25_07_31-11_08_30 OPERATOR : Benjamin; SITE : KIT | SETUP : KIT_TEST_SETUP_1 ------------------------------------------------------------ | FEB_SN : 4213| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B ------------------------------------------------------------ ------------------------------------------------------------ VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.8146', '1.846', '1.2730'] VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0310', '1.850', '1.2920'] VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0070', '1.850', '0.2654']