DTL-STS tests database

FEB_4231 18.09.25 08:35:08

link: XA-000-09-004-024-010-005-11
...SMX_0.root
link: XA-000-09-004-024-013-005-03
...SMX_2.root
link: XA-000-09-004-024-016-006-08
...SMX_4.root
link: XA-000-09-004-024-016-007-08
...SMX_6.root
link: XA-000-09-004-024-004-006-02
...SMX_1.root
link: XA-000-09-004-024-013-006-03
...SMX_3.root
link: XA-000-09-004-024-004-008-02
...SMX_5.root
link: XA-000-09-004-024-010-007-11
...SMX_7.root
link: XA-000-09-004-024-010-007-11
...VddmCSAstatus.root
Info
            08:35:08:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:35:08:ST3_Shared:INFO:	                         FEB-Sensor                         
08:35:08:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:35:17:ST3_ModuleSelector:INFO:	http://web-docs.gsi.de/~dtl-sts/?m=module&n=M7DR4T1000221B2

08:35:17:ST3_ModuleSelector:INFO:	07113

08:35:17:febtest:INFO:	Testing FEB with SN 4231
08:35:19:smx_tester:INFO:	Scanning setup
08:35:19:elinks:INFO:	Disabling clock on downlink 0
08:35:19:elinks:INFO:	Disabling clock on downlink 1
08:35:19:elinks:INFO:	Disabling clock on downlink 2
08:35:19:elinks:INFO:	Disabling clock on downlink 3
08:35:19:elinks:INFO:	Disabling clock on downlink 4
08:35:19:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
08:35:19:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:35:19:elinks:INFO:	Disabling clock on downlink 0
08:35:19:elinks:INFO:	Disabling clock on downlink 1
08:35:19:elinks:INFO:	Disabling clock on downlink 2
08:35:19:elinks:INFO:	Disabling clock on downlink 3
08:35:19:elinks:INFO:	Disabling clock on downlink 4
08:35:19:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:35:19:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:35:19:elinks:INFO:	Disabling clock on downlink 0
08:35:19:elinks:INFO:	Disabling clock on downlink 1
08:35:19:elinks:INFO:	Disabling clock on downlink 2
08:35:19:elinks:INFO:	Disabling clock on downlink 3
08:35:19:elinks:INFO:	Disabling clock on downlink 4
08:35:19:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
08:35:19:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
08:35:19:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:35:19:elinks:INFO:	Disabling clock on downlink 0
08:35:19:elinks:INFO:	Disabling clock on downlink 1
08:35:19:elinks:INFO:	Disabling clock on downlink 2
08:35:19:elinks:INFO:	Disabling clock on downlink 3
08:35:19:elinks:INFO:	Disabling clock on downlink 4
08:35:19:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
08:35:19:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:35:19:elinks:INFO:	Disabling clock on downlink 0
08:35:19:elinks:INFO:	Disabling clock on downlink 1
08:35:19:elinks:INFO:	Disabling clock on downlink 2
08:35:19:elinks:INFO:	Disabling clock on downlink 3
08:35:19:elinks:INFO:	Disabling clock on downlink 4
08:35:19:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
08:35:19:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:35:19:setup_element:INFO:	Scanning clock phase
08:35:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:35:19:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:20:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
08:35:20:setup_element:INFO:	Eye window for uplink 16: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 17: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 18: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 19: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 20: ________________________________________________________________________XXXXX___
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 21: ________________________________________________________________________XXXXX___
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 24: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:35:20:setup_element:INFO:	Eye window for uplink 25: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:35:20:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:35:20:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:35:20:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:35:20:setup_element:INFO:	Eye window for uplink 30: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:35:20:setup_element:INFO:	Eye window for uplink 31: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:35:20:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
08:35:20:setup_element:INFO:	Scanning data phases
08:35:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:35:20:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:25:setup_element:INFO:	Data phase scan results for group 0, downlink 2
08:35:25:setup_element:INFO:	Eye window for uplink 16: XXXX___________________________________X
Data delay found: 21
08:35:25:setup_element:INFO:	Eye window for uplink 17: XX___________________________________XXX
Data delay found: 19
08:35:25:setup_element:INFO:	Eye window for uplink 18: XX__________________________________XXXX
Data delay found: 18
08:35:25:setup_element:INFO:	Eye window for uplink 19: XXX_________________________________XXXX
Data delay found: 19
08:35:25:setup_element:INFO:	Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
08:35:25:setup_element:INFO:	Eye window for uplink 21: XXX___________________________________XX
Data delay found: 20
08:35:25:setup_element:INFO:	Eye window for uplink 22: XX___________________________________XXX
Data delay found: 19
08:35:25:setup_element:INFO:	Eye window for uplink 23: __________________________________XXXXX_
Data delay found: 16
08:35:25:setup_element:INFO:	Eye window for uplink 24: ________XXXXX___________________________
Data delay found: 30
08:35:25:setup_element:INFO:	Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
08:35:25:setup_element:INFO:	Eye window for uplink 26: __________XXXXXX________________________
Data delay found: 32
08:35:25:setup_element:INFO:	Eye window for uplink 27: ____________XXXXXXX_____________________
Data delay found: 35
08:35:25:setup_element:INFO:	Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
08:35:25:setup_element:INFO:	Eye window for uplink 29: _____________XXXXX______________________
Data delay found: 35
08:35:25:setup_element:INFO:	Eye window for uplink 30: ________________XXXXXXX_________________
Data delay found: 39
08:35:25:setup_element:INFO:	Eye window for uplink 31: ________________XXXXX___________________
Data delay found: 38
08:35:25:setup_element:INFO:	Setting the data phase to 21 for uplink 16
08:35:25:setup_element:INFO:	Setting the data phase to 19 for uplink 17
08:35:25:setup_element:INFO:	Setting the data phase to 18 for uplink 18
08:35:25:setup_element:INFO:	Setting the data phase to 19 for uplink 19
08:35:25:setup_element:INFO:	Setting the data phase to 19 for uplink 20
08:35:25:setup_element:INFO:	Setting the data phase to 20 for uplink 21
08:35:25:setup_element:INFO:	Setting the data phase to 19 for uplink 22
08:35:25:setup_element:INFO:	Setting the data phase to 16 for uplink 23
08:35:25:setup_element:INFO:	Setting the data phase to 30 for uplink 24
08:35:25:setup_element:INFO:	Setting the data phase to 32 for uplink 25
08:35:25:setup_element:INFO:	Setting the data phase to 32 for uplink 26
08:35:25:setup_element:INFO:	Setting the data phase to 35 for uplink 27
08:35:25:setup_element:INFO:	Setting the data phase to 35 for uplink 28
08:35:25:setup_element:INFO:	Setting the data phase to 35 for uplink 29
08:35:25:setup_element:INFO:	Setting the data phase to 39 for uplink 30
08:35:25:setup_element:INFO:	Setting the data phase to 38 for uplink 31
08:35:25:setup_element:INFO:	Beginning SMX ASICs map scan
08:35:25:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:35:25:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:25:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:35:25:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:35:25:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:35:25:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:35:25:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:35:25:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:35:25:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:35:25:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:35:25:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:35:25:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:35:26:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:35:26:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:35:26:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:35:26:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:35:26:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:35:26:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:35:26:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:35:26:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:35:26:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:35:27:setup_element:INFO:	Performing Elink synchronization
08:35:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:35:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:28:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:35:28:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:35:28:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
08:35:28:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:35:28:febtest:INFO:	Init all SMX (CSA): 30
08:35:42:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:35:42:febtest:INFO:	23-00 | XA-000-09-004-024-010-005-11 |  28.2 | 1171.5
08:35:43:febtest:INFO:	30-01 | XA-000-09-004-024-004-006-02 |  34.6 | 1147.8
08:35:43:febtest:INFO:	21-02 | XA-000-09-004-024-013-005-03 |  37.7 | 1147.8
08:35:43:febtest:INFO:	28-03 | XA-000-09-004-024-013-006-03 |  31.4 | 1159.7
08:35:43:febtest:INFO:	19-04 | XA-000-09-004-024-016-006-08 |  31.4 | 1171.5
08:35:43:febtest:INFO:	26-05 | XA-000-09-004-024-004-008-02 |  37.7 | 1141.9
08:35:44:febtest:INFO:	17-06 | XA-000-09-004-024-016-007-08 |  28.2 | 1183.3
08:35:44:febtest:INFO:	24-07 | XA-000-09-004-024-010-007-11 |  25.1 | 1189.2
08:35:45:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:35:47:ST3_smx:INFO:	chip: 23-0 	 31.389742 C 	 1183.292940 mV
08:35:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:35:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:35:47:ST3_smx:INFO:		Electrons
08:35:47:ST3_smx:INFO:	# loops 0
08:35:48:ST3_smx:INFO:	# loops 1
08:35:50:ST3_smx:INFO:	# loops 2
08:35:51:ST3_smx:INFO:	Total # of broken channels: 0
08:35:51:ST3_smx:INFO:	List of broken channels: []
08:35:51:ST3_smx:INFO:	Total # of broken channels: 0
08:35:51:ST3_smx:INFO:	List of broken channels: []
08:35:53:ST3_smx:INFO:	chip: 30-1 	 34.556970 C 	 1159.654860 mV
08:35:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:35:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:35:53:ST3_smx:INFO:		Electrons
08:35:53:ST3_smx:INFO:	# loops 0
08:35:55:ST3_smx:INFO:	# loops 1
08:35:57:ST3_smx:INFO:	# loops 2
08:35:58:ST3_smx:INFO:	Total # of broken channels: 0
08:35:58:ST3_smx:INFO:	List of broken channels: []
08:35:58:ST3_smx:INFO:	Total # of broken channels: 0
08:35:58:ST3_smx:INFO:	List of broken channels: []
08:36:00:ST3_smx:INFO:	chip: 21-2 	 37.726682 C 	 1165.571835 mV
08:36:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:00:ST3_smx:INFO:		Electrons
08:36:00:ST3_smx:INFO:	# loops 0
08:36:02:ST3_smx:INFO:	# loops 1
08:36:03:ST3_smx:INFO:	# loops 2
08:36:05:ST3_smx:INFO:	Total # of broken channels: 0
08:36:05:ST3_smx:INFO:	List of broken channels: []
08:36:05:ST3_smx:INFO:	Total # of broken channels: 0
08:36:05:ST3_smx:INFO:	List of broken channels: []
08:36:07:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1177.390875 mV
08:36:07:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:07:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:07:ST3_smx:INFO:		Electrons
08:36:07:ST3_smx:INFO:	# loops 0
08:36:08:ST3_smx:INFO:	# loops 1
08:36:10:ST3_smx:INFO:	# loops 2
08:36:12:ST3_smx:INFO:	Total # of broken channels: 1
08:36:12:ST3_smx:INFO:	List of broken channels: [1]
08:36:12:ST3_smx:INFO:	Total # of broken channels: 1
08:36:12:ST3_smx:INFO:	List of broken channels: [1]
08:36:14:ST3_smx:INFO:	chip: 19-4 	 31.389742 C 	 1183.292940 mV
08:36:14:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:14:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:14:ST3_smx:INFO:		Electrons
08:36:14:ST3_smx:INFO:	# loops 0
08:36:15:ST3_smx:INFO:	# loops 1
08:36:17:ST3_smx:INFO:	# loops 2
08:36:18:ST3_smx:INFO:	Total # of broken channels: 0
08:36:18:ST3_smx:INFO:	List of broken channels: []
08:36:18:ST3_smx:INFO:	Total # of broken channels: 0
08:36:18:ST3_smx:INFO:	List of broken channels: []
08:36:20:ST3_smx:INFO:	chip: 26-5 	 37.726682 C 	 1153.732915 mV
08:36:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:20:ST3_smx:INFO:		Electrons
08:36:20:ST3_smx:INFO:	# loops 0
08:36:21:ST3_smx:INFO:	# loops 1
08:36:23:ST3_smx:INFO:	# loops 2
08:36:24:ST3_smx:INFO:	Total # of broken channels: 0
08:36:24:ST3_smx:INFO:	List of broken channels: []
08:36:24:ST3_smx:INFO:	Total # of broken channels: 0
08:36:24:ST3_smx:INFO:	List of broken channels: []
08:36:26:ST3_smx:INFO:	chip: 17-6 	 31.389742 C 	 1195.082160 mV
08:36:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:26:ST3_smx:INFO:		Electrons
08:36:26:ST3_smx:INFO:	# loops 0
08:36:28:ST3_smx:INFO:	# loops 1
08:36:29:ST3_smx:INFO:	# loops 2
08:36:31:ST3_smx:INFO:	Total # of broken channels: 0
08:36:31:ST3_smx:INFO:	List of broken channels: []
08:36:31:ST3_smx:INFO:	Total # of broken channels: 0
08:36:31:ST3_smx:INFO:	List of broken channels: []
08:36:32:ST3_smx:INFO:	chip: 24-7 	 28.225000 C 	 1195.082160 mV
08:36:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:36:33:ST3_smx:INFO:		Electrons
08:36:33:ST3_smx:INFO:	# loops 0
08:36:34:ST3_smx:INFO:	# loops 1
08:36:36:ST3_smx:INFO:	# loops 2
08:36:37:ST3_smx:INFO:	Total # of broken channels: 0
08:36:37:ST3_smx:INFO:	List of broken channels: []
08:36:37:ST3_smx:INFO:	Total # of broken channels: 0
08:36:37:ST3_smx:INFO:	List of broken channels: []
08:36:38:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:36:38:febtest:INFO:	23-00 | XA-000-09-004-024-010-005-11 |  34.6 | 1201.0
08:36:38:febtest:INFO:	30-01 | XA-000-09-004-024-004-006-02 |  37.7 | 1177.4
08:36:38:febtest:INFO:	21-02 | XA-000-09-004-024-013-005-03 |  40.9 | 1183.3
08:36:38:febtest:INFO:	28-03 | XA-000-09-004-024-013-006-03 |  34.6 | 1195.1
08:36:39:febtest:INFO:	19-04 | XA-000-09-004-024-016-006-08 |  34.6 | 1201.0
08:36:39:febtest:INFO:	26-05 | XA-000-09-004-024-004-008-02 |  40.9 | 1171.5
08:36:39:febtest:INFO:	17-06 | XA-000-09-004-024-016-007-08 |  31.4 | 1212.7
08:36:39:febtest:INFO:	24-07 | XA-000-09-004-024-010-007-11 |  28.2 | 1218.6
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_09_18-08_35_08
OPERATOR  : Benjamin; 
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4231| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_ID:	07113

MODULE_NAME:	http://web-docs.gsi.de/~dtl-sts/?m=module&n=M7DR4T1000221B2

MODULE_TYPE:	
MODULE_LADDER:	
MODULE_MODULE:	
MODULE_SIZE:	0
MODULE_GRADE:	
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.451', '1.5350', '1.846', '2.4680']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0140', '1.850', '2.5820']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9920', '1.850', '0.5282']
Comment