DTL-STS tests database

FEB_4237 16.09.25 07:42:01

link: XA-000-09-004-024-005-009-15
...SMX_0.root
link: XA-000-09-004-024-011-010-06
...SMX_2.root
link: XA-000-09-004-024-008-008-08
...SMX_4.root
link: XA-000-09-004-024-008-009-08
...SMX_6.root
link: XA-000-09-004-024-008-012-08
...SMX_1.root
link: XA-000-09-004-024-014-013-13
...SMX_3.root
link: XA-000-09-004-024-017-013-05
...SMX_5.root
link: XA-000-09-004-024-005-008-15
...SMX_7.root
link: XA-000-09-004-024-005-008-15
...VddmCSAstatus.root
Info
            07:42:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:42:01:ST3_Shared:INFO:	                       FEB-Microcable                       
07:42:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:42:01:febtest:INFO:	Testing FEB with SN 4237
07:42:03:smx_tester:INFO:	Scanning setup
07:42:03:elinks:INFO:	Disabling clock on downlink 0
07:42:03:elinks:INFO:	Disabling clock on downlink 1
07:42:03:elinks:INFO:	Disabling clock on downlink 2
07:42:03:elinks:INFO:	Disabling clock on downlink 3
07:42:03:elinks:INFO:	Disabling clock on downlink 4
07:42:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:03:elinks:INFO:	Disabling clock on downlink 0
07:42:03:elinks:INFO:	Disabling clock on downlink 1
07:42:03:elinks:INFO:	Disabling clock on downlink 2
07:42:03:elinks:INFO:	Disabling clock on downlink 3
07:42:03:elinks:INFO:	Disabling clock on downlink 4
07:42:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:42:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:03:elinks:INFO:	Disabling clock on downlink 0
07:42:03:elinks:INFO:	Disabling clock on downlink 1
07:42:03:elinks:INFO:	Disabling clock on downlink 2
07:42:03:elinks:INFO:	Disabling clock on downlink 3
07:42:03:elinks:INFO:	Disabling clock on downlink 4
07:42:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
07:42:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
07:42:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:03:elinks:INFO:	Disabling clock on downlink 0
07:42:03:elinks:INFO:	Disabling clock on downlink 1
07:42:03:elinks:INFO:	Disabling clock on downlink 2
07:42:03:elinks:INFO:	Disabling clock on downlink 3
07:42:03:elinks:INFO:	Disabling clock on downlink 4
07:42:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
07:42:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:03:elinks:INFO:	Disabling clock on downlink 0
07:42:03:elinks:INFO:	Disabling clock on downlink 1
07:42:03:elinks:INFO:	Disabling clock on downlink 2
07:42:03:elinks:INFO:	Disabling clock on downlink 3
07:42:03:elinks:INFO:	Disabling clock on downlink 4
07:42:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
07:42:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:03:setup_element:INFO:	Scanning clock phase
07:42:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:42:04:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
07:42:04:setup_element:INFO:	Eye window for uplink 16: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 17: _______________________________________________________________________XXXXX____
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 18: ________________________________________________________________________XXXXX___
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 19: ________________________________________________________________________XXXXX___
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 20: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 21: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 22: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 23: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 24: ________________________________________________________________________XXXXX___
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 25: ________________________________________________________________________XXXXX___
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
07:42:04:setup_element:INFO:	Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
07:42:04:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
07:42:04:setup_element:INFO:	Scanning data phases
07:42:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:42:09:setup_element:INFO:	Data phase scan results for group 0, downlink 2
07:42:09:setup_element:INFO:	Eye window for uplink 16: _________________________________XXXXX__
Data delay found: 15
07:42:09:setup_element:INFO:	Eye window for uplink 17: ________________________________XXXX____
Data delay found: 13
07:42:09:setup_element:INFO:	Eye window for uplink 18: X__________________________________XXXXX
Data delay found: 17
07:42:09:setup_element:INFO:	Eye window for uplink 19: XX_________________________________XXXXX
Data delay found: 18
07:42:09:setup_element:INFO:	Eye window for uplink 20: ___________________________________XXXX_
Data delay found: 16
07:42:09:setup_element:INFO:	Eye window for uplink 21: X___________________________________XXXX
Data delay found: 18
07:42:09:setup_element:INFO:	Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
07:42:09:setup_element:INFO:	Eye window for uplink 23: _______________________________XXXXX____
Data delay found: 13
07:42:09:setup_element:INFO:	Eye window for uplink 24: _______XXXXXXX__________________________
Data delay found: 30
07:42:09:setup_element:INFO:	Eye window for uplink 25: _________XXXXXX_________________________
Data delay found: 31
07:42:09:setup_element:INFO:	Eye window for uplink 26: _________XXXXXX_________________________
Data delay found: 31
07:42:09:setup_element:INFO:	Eye window for uplink 27: ___________XXXXXXX______________________
Data delay found: 34
07:42:09:setup_element:INFO:	Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
07:42:09:setup_element:INFO:	Eye window for uplink 29: _____________XXXXX______________________
Data delay found: 35
07:42:09:setup_element:INFO:	Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
07:42:09:setup_element:INFO:	Eye window for uplink 31: _____________XXX________________________
Data delay found: 34
07:42:09:setup_element:INFO:	Setting the data phase to 15 for uplink 16
07:42:09:setup_element:INFO:	Setting the data phase to 13 for uplink 17
07:42:09:setup_element:INFO:	Setting the data phase to 17 for uplink 18
07:42:09:setup_element:INFO:	Setting the data phase to 18 for uplink 19
07:42:09:setup_element:INFO:	Setting the data phase to 16 for uplink 20
07:42:09:setup_element:INFO:	Setting the data phase to 18 for uplink 21
07:42:09:setup_element:INFO:	Setting the data phase to 15 for uplink 22
07:42:09:setup_element:INFO:	Setting the data phase to 13 for uplink 23
07:42:09:setup_element:INFO:	Setting the data phase to 30 for uplink 24
07:42:09:setup_element:INFO:	Setting the data phase to 31 for uplink 25
07:42:09:setup_element:INFO:	Setting the data phase to 31 for uplink 26
07:42:09:setup_element:INFO:	Setting the data phase to 34 for uplink 27
07:42:09:setup_element:INFO:	Setting the data phase to 35 for uplink 28
07:42:09:setup_element:INFO:	Setting the data phase to 35 for uplink 29
07:42:09:setup_element:INFO:	Setting the data phase to 35 for uplink 30
07:42:09:setup_element:INFO:	Setting the data phase to 34 for uplink 31
07:42:09:setup_element:INFO:	Beginning SMX ASICs map scan
07:42:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:42:09:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
07:42:09:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
07:42:09:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
07:42:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
07:42:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
07:42:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
07:42:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
07:42:09:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
07:42:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
07:42:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
07:42:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
07:42:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
07:42:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
07:42:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
07:42:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
07:42:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
07:42:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
07:42:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
07:42:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
07:42:12:setup_element:INFO:	Performing Elink synchronization
07:42:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
07:42:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
07:42:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
07:42:12:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
07:42:12:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
07:42:12:febtest:INFO:	Init all SMX (CSA): 30
07:42:28:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:42:29:febtest:INFO:	23-00 | XA-000-09-004-024-005-009-15 |  28.2 | 1189.2
07:42:29:febtest:INFO:	30-01 | XA-000-09-004-024-008-012-08 |  21.9 | 1201.0
07:42:29:febtest:INFO:	21-02 | XA-000-09-004-024-011-010-06 |  28.2 | 1189.2
07:42:29:febtest:INFO:	28-03 | XA-000-09-004-024-014-013-13 |  34.6 | 1159.7
07:42:30:febtest:INFO:	19-04 | XA-000-09-004-024-008-008-08 |  34.6 | 1165.6
07:42:30:febtest:INFO:	26-05 | XA-000-09-004-024-017-013-05 |  21.9 | 1218.6
07:42:30:febtest:INFO:	17-06 | XA-000-09-004-024-008-009-08 |  40.9 | 1153.7
07:42:30:febtest:INFO:	24-07 | XA-000-09-004-024-005-008-15 |  37.7 | 1153.7
07:42:31:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
07:42:33:ST3_smx:INFO:	chip: 23-0 	 28.225000 C 	 1200.969315 mV
07:42:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:33:ST3_smx:INFO:		Electrons
07:42:33:ST3_smx:INFO:	# loops 0
07:42:35:ST3_smx:INFO:	# loops 1
07:42:37:ST3_smx:INFO:	# loops 2
07:42:38:ST3_smx:INFO:	Total # of broken channels: 1
07:42:38:ST3_smx:INFO:	List of broken channels: [55]
07:42:38:ST3_smx:INFO:	Total # of broken channels: 1
07:42:38:ST3_smx:INFO:	List of broken channels: [55]
07:42:40:ST3_smx:INFO:	chip: 30-1 	 21.902970 C 	 1212.728715 mV
07:42:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:40:ST3_smx:INFO:		Electrons
07:42:40:ST3_smx:INFO:	# loops 0
07:42:42:ST3_smx:INFO:	# loops 1
07:42:44:ST3_smx:INFO:	# loops 2
07:42:46:ST3_smx:INFO:	Total # of broken channels: 1
07:42:46:ST3_smx:INFO:	List of broken channels: [66]
07:42:46:ST3_smx:INFO:	Total # of broken channels: 1
07:42:46:ST3_smx:INFO:	List of broken channels: [66]
07:42:47:ST3_smx:INFO:	chip: 21-2 	 28.225000 C 	 1206.851500 mV
07:42:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:47:ST3_smx:INFO:		Electrons
07:42:47:ST3_smx:INFO:	# loops 0
07:42:49:ST3_smx:INFO:	# loops 1
07:42:51:ST3_smx:INFO:	# loops 2
07:42:53:ST3_smx:INFO:	Total # of broken channels: 0
07:42:53:ST3_smx:INFO:	List of broken channels: []
07:42:53:ST3_smx:INFO:	Total # of broken channels: 0
07:42:53:ST3_smx:INFO:	List of broken channels: []
07:42:54:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1177.390875 mV
07:42:54:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:54:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:42:54:ST3_smx:INFO:		Electrons
07:42:54:ST3_smx:INFO:	# loops 0
07:42:56:ST3_smx:INFO:	# loops 1
07:42:58:ST3_smx:INFO:	# loops 2
07:43:00:ST3_smx:INFO:	Total # of broken channels: 0
07:43:00:ST3_smx:INFO:	List of broken channels: []
07:43:00:ST3_smx:INFO:	Total # of broken channels: 1
07:43:00:ST3_smx:INFO:	List of broken channels: [83]
07:43:01:ST3_smx:INFO:	chip: 19-4 	 37.726682 C 	 1177.390875 mV
07:43:01:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:01:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:01:ST3_smx:INFO:		Electrons
07:43:01:ST3_smx:INFO:	# loops 0
07:43:03:ST3_smx:INFO:	# loops 1
07:43:05:ST3_smx:INFO:	# loops 2
07:43:07:ST3_smx:INFO:	Total # of broken channels: 0
07:43:07:ST3_smx:INFO:	List of broken channels: []
07:43:07:ST3_smx:INFO:	Total # of broken channels: 1
07:43:07:ST3_smx:INFO:	List of broken channels: [94]
07:43:08:ST3_smx:INFO:	chip: 26-5 	 21.902970 C 	 1230.330540 mV
07:43:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:08:ST3_smx:INFO:		Electrons
07:43:08:ST3_smx:INFO:	# loops 0
07:43:10:ST3_smx:INFO:	# loops 1
07:43:12:ST3_smx:INFO:	# loops 2
07:43:14:ST3_smx:INFO:	Total # of broken channels: 3
07:43:14:ST3_smx:INFO:	List of broken channels: [3, 5, 119]
07:43:14:ST3_smx:INFO:	Total # of broken channels: 4
07:43:14:ST3_smx:INFO:	List of broken channels: [3, 5, 29, 119]
07:43:15:ST3_smx:INFO:	chip: 17-6 	 44.073563 C 	 1165.571835 mV
07:43:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:15:ST3_smx:INFO:		Electrons
07:43:15:ST3_smx:INFO:	# loops 0
07:43:17:ST3_smx:INFO:	# loops 1
07:43:19:ST3_smx:INFO:	# loops 2
07:43:21:ST3_smx:INFO:	Total # of broken channels: 0
07:43:21:ST3_smx:INFO:	List of broken channels: []
07:43:21:ST3_smx:INFO:	Total # of broken channels: 0
07:43:21:ST3_smx:INFO:	List of broken channels: []
07:43:22:ST3_smx:INFO:	chip: 24-7 	 40.898880 C 	 1159.654860 mV
07:43:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:43:22:ST3_smx:INFO:		Electrons
07:43:22:ST3_smx:INFO:	# loops 0
07:43:24:ST3_smx:INFO:	# loops 1
07:43:26:ST3_smx:INFO:	# loops 2
07:43:28:ST3_smx:INFO:	Total # of broken channels: 0
07:43:28:ST3_smx:INFO:	List of broken channels: []
07:43:28:ST3_smx:INFO:	Total # of broken channels: 0
07:43:28:ST3_smx:INFO:	List of broken channels: []
07:43:28:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:43:28:febtest:INFO:	23-00 | XA-000-09-004-024-005-009-15 |  28.2 | 1253.7
07:43:29:febtest:INFO:	30-01 | XA-000-09-004-024-008-012-08 |  25.1 | 1236.2
07:43:29:febtest:INFO:	21-02 | XA-000-09-004-024-011-010-06 |  31.4 | 1224.5
07:43:29:febtest:INFO:	28-03 | XA-000-09-004-024-014-013-13 |  37.7 | 1201.0
07:43:29:febtest:INFO:	19-04 | XA-000-09-004-024-008-008-08 |  40.9 | 1195.1
07:43:29:febtest:INFO:	26-05 | XA-000-09-004-024-017-013-05 |  25.1 | 1253.7
07:43:30:febtest:INFO:	17-06 | XA-000-09-004-024-008-009-08 |  44.1 | 1195.1
07:43:30:febtest:INFO:	24-07 | XA-000-09-004-024-005-008-15 |  44.1 | 1183.3
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_09_16-07_42_01
OPERATOR  : Benjamin; 
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4237| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4650', '1.847', '2.0320']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0110', '1.850', '2.5570']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9790', '1.850', '0.5203']
Comment