FEB_4305 25.11.25 10:23:25
Info
10:23:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:23:25:ST3_Shared:INFO: FEB-Microcable
10:23:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:23:25:febtest:INFO: Testing FEB with SN 4305
10:23:26:smx_tester:INFO: Scanning setup
10:23:27:elinks:INFO: Disabling clock on downlink 0
10:23:27:elinks:INFO: Disabling clock on downlink 1
10:23:27:elinks:INFO: Disabling clock on downlink 2
10:23:27:elinks:INFO: Disabling clock on downlink 3
10:23:27:elinks:INFO: Disabling clock on downlink 4
10:23:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:23:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:23:27:elinks:INFO: Disabling clock on downlink 0
10:23:27:elinks:INFO: Disabling clock on downlink 1
10:23:27:elinks:INFO: Disabling clock on downlink 2
10:23:27:elinks:INFO: Disabling clock on downlink 3
10:23:27:elinks:INFO: Disabling clock on downlink 4
10:23:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:23:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:23:27:elinks:INFO: Disabling clock on downlink 0
10:23:27:elinks:INFO: Disabling clock on downlink 1
10:23:27:elinks:INFO: Disabling clock on downlink 2
10:23:27:elinks:INFO: Disabling clock on downlink 3
10:23:27:elinks:INFO: Disabling clock on downlink 4
10:23:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:23:27:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:23:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:23:27:elinks:INFO: Disabling clock on downlink 0
10:23:27:elinks:INFO: Disabling clock on downlink 1
10:23:27:elinks:INFO: Disabling clock on downlink 2
10:23:27:elinks:INFO: Disabling clock on downlink 3
10:23:27:elinks:INFO: Disabling clock on downlink 4
10:23:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:23:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:23:27:elinks:INFO: Disabling clock on downlink 0
10:23:27:elinks:INFO: Disabling clock on downlink 1
10:23:27:elinks:INFO: Disabling clock on downlink 2
10:23:27:elinks:INFO: Disabling clock on downlink 3
10:23:27:elinks:INFO: Disabling clock on downlink 4
10:23:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:23:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:23:27:setup_element:INFO: Scanning clock phase
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:23:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:23:27:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:23:27:setup_element:INFO: Eye window for uplink 24: XXXXX_______________________________________________________________XXXXXXXXXXXX
Clock Delay: 36
10:23:27:setup_element:INFO: Eye window for uplink 25: XXXXX_______________________________________________________________XXXXXXXXXXXX
Clock Delay: 36
10:23:27:setup_element:INFO: Eye window for uplink 26: XXXX__________________________________________________________________XXXXXXXXXX
Clock Delay: 36
10:23:27:setup_element:INFO: Eye window for uplink 27: XXXX__________________________________________________________________XXXXXXXXXX
Clock Delay: 36
10:23:27:setup_element:INFO: Eye window for uplink 28: XXXXX___________________________________________________________________________
Clock Delay: 42
10:23:27:setup_element:INFO: Eye window for uplink 29: XXXXX___________________________________________________________________________
Clock Delay: 42
10:23:27:setup_element:INFO: Eye window for uplink 30: XXXXX___________________________________________________________________________
Clock Delay: 42
10:23:27:setup_element:INFO: Eye window for uplink 31: XXXXX___________________________________________________________________________
Clock Delay: 42
10:23:27:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 2
10:23:27:setup_element:INFO: Scanning data phases
10:23:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:23:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:23:33:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:23:33:setup_element:INFO: Eye window for uplink 24: _____XXXXXX_____________________________
Data delay found: 27
10:23:33:setup_element:INFO: Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
10:23:33:setup_element:INFO: Eye window for uplink 26: ______XXXXXXXXXXXXX__XXXXXX_XXX____XXXXX
Data delay found: 2
10:23:33:setup_element:INFO: Eye window for uplink 27: ______XXXX_XXXXXXXX__XXXXXX_XXX____XXXXX
Data delay found: 2
10:23:33:setup_element:INFO: Eye window for uplink 28: ____________XXXXXXX_____________________
Data delay found: 35
10:23:33:setup_element:INFO: Eye window for uplink 29: ____________XXXXXX______________________
Data delay found: 34
10:23:33:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
10:23:33:setup_element:INFO: Eye window for uplink 31: ____________XXXXX_______________________
Data delay found: 34
10:23:33:setup_element:INFO: Setting the data phase to 27 for uplink 24
10:23:33:setup_element:INFO: Setting the data phase to 29 for uplink 25
10:23:33:setup_element:INFO: Setting the data phase to 2 for uplink 26
10:23:33:setup_element:INFO: Setting the data phase to 2 for uplink 27
10:23:33:setup_element:INFO: Setting the data phase to 35 for uplink 28
10:23:33:setup_element:INFO: Setting the data phase to 34 for uplink 29
10:23:33:setup_element:INFO: Setting the data phase to 35 for uplink 30
10:23:33:setup_element:INFO: Setting the data phase to 34 for uplink 31
10:23:33:setup_element:INFO: Beginning SMX ASICs map scan
10:23:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:23:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:23:33:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:23:33:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:23:33:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:23:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:23:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:23:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:23:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:23:34:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:23:34:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:23:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:23:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:23:35:setup_element:INFO: Performing Elink synchronization
10:23:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:23:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:23:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:23:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:23:35:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:23:35:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
10:23:36:febtest:INFO: Init all SMX (CSA): 30
10:23:43:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:23:43:febtest:INFO: 30-01 | XA-000-09-004-042-013-003-02 | 31.4 | 1171.5
10:23:43:febtest:INFO: 28-03 | XA-000-09-004-042-013-005-02 | 28.2 | 1189.2
10:23:44:febtest:INFO: 26-05 | XA-000-09-004-042-010-002-10 | 34.6 | 1171.5
10:23:44:febtest:INFO: 24-07 | XA-000-09-004-042-010-013-10 | 40.9 | 1135.9
10:23:45:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
10:23:47:ST3_smx:INFO: chip: 30-1 31.389742 C 1177.390875 mV
10:23:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:23:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:23:47:ST3_smx:INFO: Electrons
10:23:47:ST3_smx:INFO: # loops 0
10:23:48:ST3_smx:INFO: # loops 1
10:23:50:ST3_smx:INFO: # loops 2
10:23:53:ST3_smx:INFO: Total # of broken channels: 0
10:23:53:ST3_smx:INFO: List of broken channels: []
10:23:53:ST3_smx:INFO: Total # of broken channels: 0
10:23:53:ST3_smx:INFO: List of broken channels: []
10:23:54:ST3_smx:INFO: chip: 28-3 28.225000 C 1195.082160 mV
10:23:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:23:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:23:54:ST3_smx:INFO: Electrons
10:23:54:ST3_smx:INFO: # loops 0
10:23:56:ST3_smx:INFO: # loops 1
10:23:58:ST3_smx:INFO: # loops 2
10:24:00:ST3_smx:INFO: Total # of broken channels: 0
10:24:00:ST3_smx:INFO: List of broken channels: []
10:24:00:ST3_smx:INFO: Total # of broken channels: 0
10:24:00:ST3_smx:INFO: List of broken channels: []
10:24:01:ST3_smx:INFO: chip: 26-5 31.389742 C 1183.292940 mV
10:24:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:24:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:24:01:ST3_smx:INFO: Electrons
10:24:01:ST3_smx:INFO: # loops 0
10:24:03:ST3_smx:INFO: # loops 1
10:24:04:ST3_smx:INFO: # loops 2
10:24:06:ST3_smx:INFO: Total # of broken channels: 0
10:24:06:ST3_smx:INFO: List of broken channels: []
10:24:06:ST3_smx:INFO: Total # of broken channels: 0
10:24:06:ST3_smx:INFO: List of broken channels: []
10:24:08:ST3_smx:INFO: chip: 24-7 44.073563 C 1147.806000 mV
10:24:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:24:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:24:08:ST3_smx:INFO: Electrons
10:24:08:ST3_smx:INFO: # loops 0
10:24:09:ST3_smx:INFO: # loops 1
10:24:11:ST3_smx:INFO: # loops 2
10:24:12:ST3_smx:INFO: Total # of broken channels: 0
10:24:12:ST3_smx:INFO: List of broken channels: []
10:24:12:ST3_smx:INFO: Total # of broken channels: 0
10:24:12:ST3_smx:INFO: List of broken channels: []
10:24:13:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:24:13:febtest:INFO: 30-01 | XA-000-09-004-042-013-003-02 | 31.4 | 1206.9
10:24:13:febtest:INFO: 28-03 | XA-000-09-004-042-013-005-02 | 28.2 | 1218.6
10:24:13:febtest:INFO: 26-05 | XA-000-09-004-042-010-002-10 | 34.6 | 1206.9
10:24:13:febtest:INFO: 24-07 | XA-000-09-004-042-010-013-10 | 44.1 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_11_25-10_23_25
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4305| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.8571', '1.850', '1.3070']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0200', '1.850', '1.2970']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9960', '1.850', '0.2637']