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FEB_5500 10.10.23 13:51:13
TextEdit.txt
13:51:08:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.71
13:51:09:febtest:INFO: FEB8.2 selected
13:51:09:smx_tester:INFO: Setting Elink clock mode to 160 MHz
13:51:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:51:13:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
13:51:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:51:14:febtest:INFO: Tsting FEB with SN 5500
13:51:16:smx_tester:INFO: Scanning setup
13:51:16:elinks:INFO: Disabling clock on downlink 0
13:51:16:elinks:INFO: Disabling clock on downlink 1
13:51:16:elinks:INFO: Disabling clock on downlink 2
13:51:16:elinks:INFO: Disabling clock on downlink 3
13:51:16:elinks:INFO: Disabling clock on downlink 4
13:51:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:51:16:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
13:51:16:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 1
13:51:16:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 3
13:51:16:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 4
13:51:16:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 5
13:51:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:51:16:elinks:INFO: Disabling clock on downlink 0
13:51:16:elinks:INFO: Disabling clock on downlink 1
13:51:16:elinks:INFO: Disabling clock on downlink 2
13:51:16:elinks:INFO: Disabling clock on downlink 3
13:51:16:elinks:INFO: Disabling clock on downlink 4
13:51:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:51:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:51:16:elinks:INFO: Disabling clock on downlink 0
13:51:16:elinks:INFO: Disabling clock on downlink 1
13:51:16:elinks:INFO: Disabling clock on downlink 2
13:51:16:elinks:INFO: Disabling clock on downlink 3
13:51:16:elinks:INFO: Disabling clock on downlink 4
13:51:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:51:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:51:16:elinks:INFO: Disabling clock on downlink 0
13:51:16:elinks:INFO: Disabling clock on downlink 1
13:51:16:elinks:INFO: Disabling clock on downlink 2
13:51:16:elinks:INFO: Disabling clock on downlink 3
13:51:16:elinks:INFO: Disabling clock on downlink 4
13:51:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:51:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:51:16:elinks:INFO: Disabling clock on downlink 0
13:51:16:elinks:INFO: Disabling clock on downlink 1
13:51:16:elinks:INFO: Disabling clock on downlink 2
13:51:16:elinks:INFO: Disabling clock on downlink 3
13:51:16:elinks:INFO: Disabling clock on downlink 4
13:51:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:51:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:51:16:setup_element:INFO: Scanning clock phase
13:51:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:51:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
13:51:17:setup_element:INFO: Clock phase scan results for group 0, downlink 0
13:51:17:setup_element:INFO: Eye window for uplink 0 : __________________________________________________________________XXXXXX________
Clock Delay: 28
13:51:17:setup_element:INFO: Eye window for uplink 1 : ___________________________________________________________________XXXXXX_______
Clock Delay: 29
13:51:17:setup_element:INFO: Eye window for uplink 3 : __________________________________________________________________XXXXXX________
Clock Delay: 28
13:51:17:setup_element:INFO: Eye window for uplink 4 : __________________________________________________________________XXXXXXX_______
Clock Delay: 29
13:51:17:setup_element:INFO: Eye window for uplink 5 : __________________________________________________________________XXXXXXX_______
Clock Delay: 29
13:51:17:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 0
13:51:17:setup_element:INFO: Scanning data phases
13:51:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:51:17:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
13:51:22:setup_element:INFO: Data phase scan results for group 0, downlink 0
13:51:22:setup_element:INFO: Eye window for uplink 0 : _____________________________XXXX_______
Data delay found: 10
13:51:22:setup_element:INFO: Eye window for uplink 1 : ____________________________XXXX________
Data delay found: 9
13:51:22:setup_element:INFO: Eye window for uplink 3 : _____________________________XXXXX______
Data delay found: 11
13:51:22:setup_element:INFO: Eye window for uplink 4 : ___________________________________XXXX_
Data delay found: 16
13:51:22:setup_element:INFO: Eye window for uplink 5 : _________________________________XXXX___
Data delay found: 14
13:51:22:setup_element:INFO: Setting the data phase to 10 for uplink 0
13:51:22:setup_element:INFO: Setting the data phase to 9 for uplink 1
13:51:22:setup_element:INFO: Setting the data phase to 11 for uplink 3
13:51:22:setup_element:INFO: Setting the data phase to 16 for uplink 4
13:51:22:setup_element:INFO: Setting the data phase to 14 for uplink 5
13:51:22:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 3, 4, 5]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 73
Eye Windows:
Uplink 0: __________________________________________________________________XXXXXX________
Uplink 1: ___________________________________________________________________XXXXXX_______
Uplink 3: __________________________________________________________________XXXXXX________
Uplink 4: __________________________________________________________________XXXXXXX_______
Uplink 5: __________________________________________________________________XXXXXXX_______
Data phase characteristics:
Uplink 0:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 1:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 3:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 4:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 5:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
]
13:51:22:setup_element:INFO: Beginning SMX ASICs map scan
13:51:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:51:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
13:51:22:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
13:51:22:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
13:51:22:uplink:INFO: Setting uplinks mask [0, 1, 3, 4, 5]
13:51:22:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 4
13:51:22:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 0
13:51:22:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 5
13:51:22:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 1
13:51:23:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 3
13:51:24:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 3, 4, 5]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 4)
ASIC address 0x1: (ASIC uplink, uplink): (0, 0)
ASIC address 0x2: (ASIC uplink, uplink): (0, 5)
ASIC address 0x3: (ASIC uplink, uplink): (0, 1)
ASIC address 0x7: (ASIC uplink, uplink): (0, 3)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 73
Eye Windows:
Uplink 0: __________________________________________________________________XXXXXX________
Uplink 1: ___________________________________________________________________XXXXXX_______
Uplink 3: __________________________________________________________________XXXXXX________
Uplink 4: __________________________________________________________________XXXXXXX_______
Uplink 5: __________________________________________________________________XXXXXXX_______
Data phase characteristics:
Uplink 0:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 1:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 3:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 4:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 5:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
13:51:24:setup_element:INFO: Performing Elink synchronization
13:51:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:51:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
13:51:24:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
13:51:24:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
13:51:24:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
13:51:24:uplink:INFO: Enabling uplinks [0, 1, 3, 4, 5]
13:51:25:ST3_emu:INFO: Number of chips: 5
13:51:25:ST3_emu:INFO: Chip address: 0x0
13:51:25:ST3_emu:INFO: Chip address: 0x1
13:51:25:ST3_emu:INFO: Chip address: 0x2
13:51:25:ST3_emu:INFO: Chip address: 0x3
13:51:25:ST3_emu:INFO: Chip address: 0x7
13:51:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:51:26:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 56.8 | 1106.2
13:51:26:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 34.6 | 1195.1
13:51:26:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 40.9 | 1159.7
13:51:27:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 37.7 | 1183.3
13:51:27:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1195.1
13:51:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:51:30:ST3_smx:INFO: chip: 0-0 53.612520 C 1106.178435 mV
13:51:30:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:51:30:ST3_smx:INFO: Electrons
13:51:30:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:32:ST3_smx:INFO: ----> Checking Analog response
13:51:32:ST3_smx:INFO: ----> Checking broken channels
13:51:33:ST3_smx:INFO: Total # broken ch: 128
13:51:33:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:33:ST3_smx:INFO: List SLOW: []
13:51:33:ST3_smx:INFO: Holes
13:51:33:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:35:ST3_smx:INFO: ----> Checking Analog response
13:51:35:ST3_smx:INFO: ----> Checking broken channels
13:51:35:ST3_smx:INFO: Total # broken ch: 128
13:51:35:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:35:ST3_smx:INFO: List SLOW: []
13:51:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:51:35:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 56.8 | 1100.2
13:51:36:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 34.6 | 1195.1
13:51:36:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 40.9 | 1159.7
13:51:36:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 37.7 | 1183.3
13:51:36:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1195.1
13:51:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:51:41:ST3_smx:INFO: chip: 0-1 34.556970 C 1189.190035 mV
13:51:41:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:51:41:ST3_smx:INFO: Electrons
13:51:41:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:43:ST3_smx:INFO: ----> Checking Analog response
13:51:43:ST3_smx:INFO: ----> Checking broken channels
13:51:43:ST3_smx:INFO: Total # broken ch: 127
13:51:43:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:43:ST3_smx:INFO: List SLOW: []
13:51:43:ST3_smx:INFO: Holes
13:51:43:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:45:ST3_smx:INFO: ----> Checking Analog response
13:51:45:ST3_smx:INFO: ----> Checking broken channels
13:51:45:ST3_smx:INFO: Total # broken ch: 127
13:51:45:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:45:ST3_smx:INFO: List SLOW: []
13:51:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:51:45:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 56.8 | 1100.2
13:51:46:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 37.7 | 1183.3
13:51:46:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 37.7 | 1159.7
13:51:46:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 37.7 | 1177.4
13:51:46:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1195.1
13:51:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:51:50:ST3_smx:INFO: chip: 0-2 34.556970 C 1165.571835 mV
13:51:50:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:51:50:ST3_smx:INFO: Electrons
13:51:50:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:52:ST3_smx:INFO: ----> Checking Analog response
13:51:52:ST3_smx:INFO: ----> Checking broken channels
13:51:53:ST3_smx:INFO: Total # broken ch: 128
13:51:53:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:53:ST3_smx:INFO: List SLOW: []
13:51:53:ST3_smx:INFO: Holes
13:51:53:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:51:54:ST3_smx:INFO: ----> Checking Analog response
13:51:54:ST3_smx:INFO: ----> Checking broken channels
13:51:55:ST3_smx:INFO: Total # broken ch: 128
13:51:55:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:51:55:ST3_smx:INFO: List SLOW: []
13:51:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:51:55:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 53.6 | 1100.2
13:51:55:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 34.6 | 1183.3
13:51:55:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 37.7 | 1159.7
13:51:56:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 37.7 | 1177.4
13:51:56:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1195.1
13:51:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:52:00:ST3_smx:INFO: chip: 0-3 37.726682 C 1165.571835 mV
13:52:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:52:00:ST3_smx:INFO: Electrons
13:52:00:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:52:02:ST3_smx:INFO: ----> Checking Analog response
13:52:02:ST3_smx:INFO: ----> Checking broken channels
13:52:02:ST3_smx:INFO: Total # broken ch: 127
13:52:02:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:52:02:ST3_smx:INFO: List SLOW: []
13:52:02:ST3_smx:INFO: Holes
13:52:02:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:52:04:ST3_smx:INFO: ----> Checking Analog response
13:52:04:ST3_smx:INFO: ----> Checking broken channels
13:52:05:ST3_smx:INFO: Total # broken ch: 127
13:52:05:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:52:05:ST3_smx:INFO: List SLOW: []
13:52:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:52:05:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 53.6 | 1100.2
13:52:05:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 37.7 | 1183.3
13:52:05:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 37.7 | 1159.7
13:52:06:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 40.9 | 1165.6
13:52:06:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1189.2
13:52:06:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:52:10:ST3_smx:INFO: chip: 0-7 31.389742 C 1189.190035 mV
13:52:10:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:52:10:ST3_smx:INFO: Electrons
13:52:10:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:52:12:ST3_smx:INFO: ----> Checking Analog response
13:52:12:ST3_smx:INFO: ----> Checking broken channels
13:52:12:ST3_smx:INFO: Total # broken ch: 128
13:52:12:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:52:12:ST3_smx:INFO: List SLOW: []
13:52:12:ST3_smx:INFO: Holes
13:52:12:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
13:52:14:ST3_smx:INFO: ----> Checking Analog response
13:52:14:ST3_smx:INFO: ----> Checking broken channels
13:52:15:ST3_smx:INFO: Total # broken ch: 128
13:52:15:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
13:52:15:ST3_smx:INFO: List SLOW: []
13:52:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:52:15:febtest:INFO: 0-0 | XA-000-08-003-000-001-179-10 | 53.6 | 1100.2
13:52:15:febtest:INFO: 0-1 | XA-000-08-001-064-043-208-12 | 37.7 | 1183.3
13:52:15:febtest:INFO: 0-2 | XA-000-08-003-000-001-180-10 | 37.7 | 1159.7
13:52:16:febtest:INFO: 0-3 | XA-000-08-001-064-043-200-11 | 40.9 | 1165.6
13:52:16:febtest:INFO: 0-7 | XA-000-08-001-064-041-160-03 | 34.6 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_10-13_51_13', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Test', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-001-064-041-160-03', 'FUSED_ID': 6359364698915379715, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 128, 'N_BROKEN_FAST': '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 128, 'P_BROKEN_FAST': '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.450', '1.3850', '1.850', '1.9160', '0.000', '0.0000', '7.000', '0.7773'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 0, 'ADC_VREF_P': 63, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 64}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 0, 'ADC_VREF_P': 63, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 64}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 0, 'ADC_VREF_P': 63, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 64}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 0, 'ADC_VREF_P': 63, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 64}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 0, 'ADC_VREF_P': 63, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 64}
===============================
13:52:41:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_5500/TestDate_2023_10_10-13_51_13/