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s_setup.h
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1 // $Id: s_setup.h 3340 2021-10-18 13:10:25Z linev $
2 //-----------------------------------------------------------------------
3 // The GSI Online Offline Object Oriented (Go4) Project
4 // Experiment Data Processing at EE department, GSI
5 //-----------------------------------------------------------------------
6 // Copyright (C) 2000- GSI Helmholtzzentrum fuer Schwerionenforschung GmbH
7 // Planckstr. 1, 64291 Darmstadt, Germany
8 // Contact: http://go4.gsi.de
9 //-----------------------------------------------------------------------
10 // This software can be used under the license agreements as stated
11 // in Go4License.txt file which is part of the distribution.
12 //-----------------------------------------------------------------------
13 
14 #ifndef S_SETUP_H
15 #define S_SETUP_H
16 
17 #include "typedefs.h"
18 
19 #include "sbs_def.h"
20 
21 /*
22  * N. Kurz
23  * global SBS setup parameter structure
24  */
25 
26 /* After allocating s_setup, set in f_ut_setup_ini */
27 /* ps_setup->l_endian = 1; */
28 /* ps_setup->l_version = n; */
29 /* ps_setup->bl_struc_len = sizeof(s_setup)/4; */
30 /* ps_setup->l_fix_lw = ((int)&lp_rem_mem_base[0]-(int)ps_setup)/4; */
31 /* ps_setup->bl_sbs__n_cr = SBS__N_CR; */
32 /* ps_setup->bl_sbs__n_trg_typ = SBS__N_TRG_TYP; */
33 
34 /* JAM note that actual setup structure depends on architecture of client machine
35  * ADDRS can be 4 or 8 byte. So we need auxiliary structures to receive
36  * setup from any architecture */
37 
38 typedef struct
39 {
40 /*---------------------------------------------------------------------------*/
41 INTU4 l_endian; /* set to 1 */
42 INTU4 l_version; /* increment in f_ut_setup_ini after changes */
43 INTU4 bl_struc_len; /* sizeof(s_setup)/4 : length of this structure */
44 INTU4 l_fix_lw; /* (&lp_rem_mem_base-ps_setup)/4 : swapping size */
45 INTU4 bl_sbs__n_cr; /* set to SBS__N_CR */
46 INTU4 bl_sbs__n_trg_typ; /* set to SBS__N_TRG_TYP */
47 /*---------------------------------------------------------------------------*/
48 INTU4 bi_master; /* indicates type of master event builder */
49  /* meb: 1 = CVC, 2 = E6, 3 = E7 */
50 INTU4 bl_no_crates; /* Number of crates to read (bh_rd_flg > 0) */
51 INTU4 bh_crate_nr; /* crate nr. of readout processor: meb = 0, slave = 1-15 */
52  /* this value will be set by the load setup command and */
53  /* is not parsed from the .usf file */
54 /*---------------------------------------------------------------------------*/
55 INTU4 bl_ev_buf_len; /* length of single event buffer */
56 INTU4 bl_n_ev_buf; /* number of event buffers in a stream */
57 INTU4 bl_n_stream; /* number of streams */
58 /*---------------------------------------------------------------------------*/
59 INTU4 bi_evt_typ_sy; /* event type of synchronous events, default = 10 */
60 INTU4 bi_evt_typ_asy; /* event type of asynchronous events, default = 10 */
61 INTU4 bi_evt_subtyp_sy; /* event subtype of synchronous events, default = 1 */
62 INTU4 bi_evt_subtyp_asy; /* event subtype of asynchronous events, default = 2 */
63 INTS4 h_se_control; /* serves as branch identifier in a multi-branch system */
64 /*---------------------------------------------------------------------------*/
65 INTU4 bh_rd_typ; /* 0 = standard readout with readout tables */
66  /* 1 = user readout (function) */
67  /* if the following bh_meb_asy_flg is set to 1 there will be a second */
68  /* async. subevent pipe installed, which will be collected by the meb */
69  /* collector, but must be filled by a seperate process */
70 INTU4 bh_col_mode; /* indicates mode of this MEB collector or master readout:*/
71  /* 0 = standard, the collector formats events and passes */
72  /* the formatted event buffer streams to the */
73  /* transport */
74  /* 1 = collector collects subevents from the various */
75  /* SBS pipes, but no event formatting will be done. */
76  /* instead the collected subevents are written into a */
77  /* output pipe for the next layer node of the */
78  /* multi-branch multi-layer daq system. this mode */
79  /* requires bl_ml_pipe_base_addr, bl_ml_pipe_seg_len */
80  /* and bl_ml_pipe_len to be specified (see below). */
81  /* 2 = only m_read_meb and no collector runs on the */
82  /* SBS master (MEB). Its subevent pipe will be read */
83  /* by a node of the multi-branch multi-layer daq */
84  /* system. in this case the mb ml node gets the pipe */
85  /* specs from bl_pipe_seg_len and bl_pipe_len */
86  /* (see above). */
87  /* 3 = includes both 0 and 1 mode. */
88 /*---------------------------------------------------------------------------*/
89 ADDRS bl_loc_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
90  /* window on the local crate JAM64*/
91 ADDRS bl_rem_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
92  /* window on the remote crate JAM64*/
93 INTU4 bl_esone_off; /* offset from standard to ESONE window in bytes */
94 INTU4 bl_cvc_crr_off; /* offset from to the CVC CAMAC Read Register */
95 INTU4 bl_cvc_csr_off; /* offset to the CVC Control and Status Register */
96 INTU4 bl_cvc_clb_off; /* offset to the CVC CAMAC Lam Buffer */
97 INTU4 bl_se_meb_asy_len; /* length of the async. pipe of the master, including */
98  /* control and data */
99 INTU4 bh_meb_asy_flg; /* indicates if meb must collect must an async. pipe */
100  /* residing on the meb: 0 = no, 1 = yes */
101 
102 ADDRS bl_ml_pipe_base_addr;/* base address of the multi-branch multi-layer daq JAM64 */
103  /* system output pipe. */
104  /* only requested ig bh_col_mode = 1,2 */
105 
106 ADDRS bl_ml_pipe_seg_len; /* length of the multi-branch multi-layer daq system JAM64 */
107  /* output pipe. (total lengt of subevent pipe) */
108  /* only requested ig bh_col_mode = 1,2 */
109 
110 INTU4 bl_ml_pipe_len; /* number of subevent/fragment slots in the multi-branch */
111  /* multi-layer daq system output pipe */
112  /* only requested ig bh_col_mode = 1,2 */
113 INTU4 bl_n_col_retry; /* number of retries the subevent collect process makes */
114  /* until giving up time slice */
115 /*---------------------------------------------------------------------------*/
116 INTU4 bh_meb_trig_mode; /* if this is set to NON zero a special mode is requested */
117  /* for the trigger module serving m_read_meb. */
118  /* this could be: */
119  /* NOT irq (LAM, VME irq) */
120  /* or NOT standard base address (VME) */
121  /* or NOT local crate */
122  /* if bh_meb_trig_mode is NOT 0 always the following two */
123  /* setup paramters will be taken for type and base addr. */
124  /* */
125  /* NOTE: the fast clear and conversion time will be taken */
126  /* from bl_trig_fct[0] and bl_trig_cvt[0] from this */
127  /* setup structure */
128  /* */
129  /* 0 = standard = local interrupt (CAMAC LAM, VME IRQ) */
130  /* 1 = special: local interrupt (CAMAC LAM, VME IRQ) */
131  /* 2 = special: remote VSB interrupt (not yet impleme) */
132  /* 3 = special: polling */
134  /* 1 = CAMAC type trigger module */
135  /* 2 = VME type trigger module */
136  /* 3 = FASTBUS type triggermodule */
137 
139  /* base address of trigger module acting together with */
140  /* m_read_meb if bh_meb_trig_mode != 0 */
141  /* NOTE: if trigger module is remote the complete (VSB) */
142  /* base address must be specified. example: */
143  /* f0580000 for a CAMAC trigger module in crate 2 */
144  /* serving m_read_meb running on an E7 in a VME */
145  /* crate. (see sketch at end of this file)
146  * JAM64 changed type to ADDRS*/
147 
148 
149 /*---------------------------------------------------------------------------*/
150 INTU4 lp_cvc_irq; /* start address of the CVC irq physical segment */
151 INTU4 bl_cvc_irq_len; /* length of CVC irq phys. segment */
152 INTU4 bl_cvc_irq_source_off;/* offset from lp_cvc_irq to the CVC irq source register */
153 INTU4 bl_cvc_irq_mask_off; /* offset from lp_cvc_irq to the CVC irq mask register */
154 /*---------------------------------------------------------------------------*/
155 /* all values in this section will be initalized by a loader task */
156 INTS4 h_rd_tab_flg; /* -1 = init and readout tables invalid (this is set by */
157  /* the write_sbs_setup task */
158  /* 0 = init and readout tables have to be modified to */
159  /* virtual cnafs */
160  /* 1 = this modification is done and must not be done */
161  /* before a new table was loaded */
162 INTU4 bl_init_read_len; /* total length of init and readout CAMAC cnaf list for */
163  /* all crates and trigger types (in bytes) */
164 /* ------------------ end of fixed block --------------------------*/
165 /*---------------------------------------------------------------------------*/
166 
167 
168 ADDRS lp_rem_mem_base[SBS__N_CR];
169  /* physical base address for accessing slave crate memory */
170  /* seen from the MEB (pipes). This could be the VSB */
171  /* base address for accessing remote crates */
172 ADDRS bl_rem_mem_off[SBS__N_CR];
173  /* offset from lp_rem_mem_base[SBS__N_CR] to the memory */
174  /* space of the remote slaves (seen from MEB) */
175 ADDRS bl_rem_mem_len[SBS__N_CR];
176  /* lenght of the memory address window with the physical */
177  /* base adress lp_rem_mem_base[SBS__N_CR] */
178 
179 
180 /*---------------------------------------------------------------------------*/
181 ADDRS lp_rem_cam_base[SBS__N_CR];
182  /* physical base address for accessing slave directly via CAMAC JAM64: replaced INTU4 */
183 ADDRS bl_rem_cam_off[SBS__N_CR];
184  /* offset from lp_rem_cam_base[SBS__N_CR] to the remote */
185  /* CAMAC space of the slaves (seen from MEB). JAM64: replaced INTU4 */
186 INTU4 bl_rem_cam_len[SBS__N_CR];
187  /* lenght of the CAMAC address window with the physical */
188 /*---------------------------------------------------------------------------*/
189 ADDRS lp_loc_mem_base[SBS__N_CR];
190  /* base address for accessing local crate. (could be for */
191  /* example local CAMAC base or extended VME base.) JAM64: replaced INTU4 */
192 ADDRS bl_loc_mem_len[SBS__N_CR];
193  /* length of physical segment for accessing local crate */
194  /* starting from lp_loc_mem_base[SBS__N_CR]. JAM64: replaced INTU4 */
195 /*---------------------------------------------------------------------------*/
196 INTU4 l_loc_pipe_type[SBS__N_CR];
197  /* type of subevent pipe: 0: with smem_create */
198  /* 1: direct mapping */
199 ADDRS lp_loc_pipe_base[SBS__N_CR];
200  /* RAM start address of the crate controller (used for */
201  /* location of subevent pipe) JAM64: replaced INTU4 */
202 ADDRS bl_pipe_off[SBS__N_CR];
203  /* offset from lp_ram_loc_start to start of the remote */
204  /* communication segment slave <-> master seen from the */
205  /* slave in bytes = start of subevent pipe JAM64: replaced INTU4 */
206 ADDRS bl_pipe_seg_len[SBS__N_CR];
207  /* length of the remote communication segment in bytes */
208  /* = total lengt of subevent pipe JAM64: replaced INTU4 */
209 INTU4 bl_pipe_len[SBS__N_CR]; /* number of subevent slots in a pipe */
210 INTU4 bh_controller_id[SBS__N_CR];
211  /* bh_controller_id MUST be set for ESONE CNAF execution */
212  /* 1 = CVC, 2 = E6, 3 = E7, 4 = AEB, 5 = CBV, 6 = CVI */
213  /* 7 = CAV (Q and X inverted) */
214 INTU4 bh_sy_asy_flg[SBS__N_CR];
215  /* indicates if this crate must be readout synchronous */
216  /* or asynchronous: 0 = synchronous, 1 = asynchronous */
217  /* this flag is only valid for crates with intelligent */
218  /* controller. At this point it is decided wether a crate */
219  /* is readout sync. or async. */
220 INTU4 bh_trig_stat_nr[SBS__N_CR];/* CAMAC station nr. of the trigger module, must be 1 */
221 INTU4 bl_trig_cvt[SBS__N_CR]; /* conversion time of trigger module */
222 INTU4 bl_trig_fct[SBS__N_CR]; /* fast clear acceptance time of trigger module */
223 INTS4 i_se_typ[SBS__N_CR]; /* subevent typ, default = 10 */
224 INTS4 i_se_subtyp[SBS__N_CR]; /* subevent subtyp: CAMAC = 1, FASTBUS = 2 */
225 INTS4 i_se_procid[SBS__N_CR]; /* subevent processor id */
226 /*---------------------------------------------------------------------------*/
227 INTU4 bh_rd_flg[SBS__N_CR];
228  /* 0 = crate not readout */
229  /* 1 = crate read out by meb */
230  /* 2 = crate readout by intelligent crate controller */
231 INTU4 bl_init_tab_off[SBS__N_CR];
232  /* offset from start of readout table segment to the */
233  /* start of the init table as a function of crate number */
234  /* (in longwords) */
235 INTU4 bi_init_tab_len[SBS__N_CR];
236  /* lenght of the init tables. if one of this values is 0 */
237  /* it means that this crate must not be not initalized */
238  /* (in longwords) */
240  /* maximal subevent length [b] of this crate and trigger */
242  /* offset from start of readout table segment to the */
243  /* start of the readout tables as a function of crate */
244  /* number and trigger type (in longwords) */
246  /* lenght of the readout tables. if one of this values */
247  /* is 0 it means that this crate for this trigger type is */
248  /* not read out (in longwords) */
249 /*---------------------------------------------------------------------------*/
250 } s_setup;
251 
252 
253 /* JAM this is a helper structure to receive a setup structure originated by
254  * a 32 bit architecture mbs node. All addresses are 4 byte, as in old MBS*/
255 
256 typedef struct
257 {
258 /*---------------------------------------------------------------------------*/
259 INTU4 l_endian; /* set to 1 */
260 INTU4 l_version; /* increment in f_ut_setup_ini after changes */
261 INTU4 bl_struc_len; /* sizeof(s_setup)/4 : length of this structure */
262 INTU4 l_fix_lw; /* (&lp_rem_mem_base-ps_setup)/4 : swapping size */
263 INTU4 bl_sbs__n_cr; /* set to SBS__N_CR */
264 INTU4 bl_sbs__n_trg_typ; /* set to SBS__N_TRG_TYP */
265 /*---------------------------------------------------------------------------*/
266 INTU4 bi_master; /* indicates type of master event builder */
267  /* meb: 1 = CVC, 2 = E6, 3 = E7 */
268 INTU4 bl_no_crates; /* Number of crates to read (bh_rd_flg > 0) */
269 INTU4 bh_crate_nr; /* crate nr. of readout processor: meb = 0, slave = 1-15 */
270  /* this value will be set by the load setup command and */
271  /* is not parsed from the .usf file */
272 /*---------------------------------------------------------------------------*/
273 INTU4 bl_ev_buf_len; /* length of single event buffer */
274 INTU4 bl_n_ev_buf; /* number of event buffers in a stream */
275 INTU4 bl_n_stream; /* number of streams */
276 /*---------------------------------------------------------------------------*/
277 INTU4 bi_evt_typ_sy; /* event type of synchronous events, default = 10 */
278 INTU4 bi_evt_typ_asy; /* event type of asynchronous events, default = 10 */
279 INTU4 bi_evt_subtyp_sy; /* event subtype of synchronous events, default = 1 */
280 INTU4 bi_evt_subtyp_asy; /* event subtype of asynchronous events, default = 2 */
281 INTS4 h_se_control; /* serves as branch identifier in a multi-branch system */
282 /*---------------------------------------------------------------------------*/
283 INTU4 bh_rd_typ; /* 0 = standard readout with readout tables */
284  /* 1 = user readout (function) */
285  /* if the following bh_meb_asy_flg is set to 1 there will be a second */
286  /* async. subevent pipe installed, which will be collected by the meb */
287  /* collector, but must be filled by a seperate process */
288 INTU4 bh_col_mode; /* indicates mode of this MEB collector or master readout:*/
289  /* 0 = standard, the collector formats events and passes */
290  /* the formatted event buffer streams to the */
291  /* transport */
292  /* 1 = collector collects subevents from the various */
293  /* SBS pipes, but no event formatting will be done. */
294  /* instead the collected subevents are written into a */
295  /* output pipe for the next layer node of the */
296  /* multi-branch multi-layer daq system. this mode */
297  /* requires bl_ml_pipe_base_addr, bl_ml_pipe_seg_len */
298  /* and bl_ml_pipe_len to be specified (see below). */
299  /* 2 = only m_read_meb and no collector runs on the */
300  /* SBS master (MEB). Its subevent pipe will be read */
301  /* by a node of the multi-branch multi-layer daq */
302  /* system. in this case the mb ml node gets the pipe */
303  /* specs from bl_pipe_seg_len and bl_pipe_len */
304  /* (see above). */
305  /* 3 = includes both 0 and 1 mode. */
306 /*---------------------------------------------------------------------------*/
307 INTU4 bl_loc_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
308  /* window on the local crate*/
309 INTU4 bl_rem_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
310  /* window on the remote crate*/
311 INTU4 bl_esone_off; /* offset from standard to ESONE window in bytes */
312 INTU4 bl_cvc_crr_off; /* offset from to the CVC CAMAC Read Register */
313 INTU4 bl_cvc_csr_off; /* offset to the CVC Control and Status Register */
314 INTU4 bl_cvc_clb_off; /* offset to the CVC CAMAC Lam Buffer */
315 INTU4 bl_se_meb_asy_len; /* length of the async. pipe of the master, including */
316  /* control and data */
317 INTU4 bh_meb_asy_flg; /* indicates if meb must collect must an async. pipe */
318  /* residing on the meb: 0 = no, 1 = yes */
319 INTU4 bl_ml_pipe_base_addr;/* base address of the multi-branch multi-layer daq */
320  /* system output pipe. */
321  /* only requested ig bh_col_mode = 1,2 */
322 INTU4 bl_ml_pipe_seg_len; /* length of the multi-branch multi-layer daq system */
323  /* output pipe. (total lengt of subevent pipe) */
324  /* only requested ig bh_col_mode = 1,2 */
325 INTU4 bl_ml_pipe_len; /* number of subevent/fragment slots in the multi-branch */
326  /* multi-layer daq system output pipe */
327  /* only requested ig bh_col_mode = 1,2 */
328 INTU4 bl_n_col_retry; /* number of retries the subevent collect process makes */
329  /* until giving up time slice */
330 /*---------------------------------------------------------------------------*/
331 INTU4 bh_meb_trig_mode; /* if this is set to NON zero a special mode is requested */
332  /* for the trigger module serving m_read_meb. */
333  /* this could be: */
334  /* NOT irq (LAM, VME irq) */
335  /* or NOT standard base address (VME) */
336  /* or NOT local crate */
337  /* if bh_meb_trig_mode is NOT 0 always the following two */
338  /* setup paramters will be taken for type and base addr. */
339  /* */
340  /* NOTE: the fast clear and conversion time will be taken */
341  /* from bl_trig_fct[0] and bl_trig_cvt[0] from this */
342  /* setup structure */
343  /* */
344  /* 0 = standard = local interrupt (CAMAC LAM, VME IRQ) */
345  /* 1 = special: local interrupt (CAMAC LAM, VME IRQ) */
346  /* 2 = special: remote VSB interrupt (not yet impleme) */
347  /* 3 = special: polling */
349  /* 1 = CAMAC type trigger module */
350  /* 2 = VME type trigger module */
351  /* 3 = FASTBUS type triggermodule */
353  /* base address of trigger module acting together with */
354  /* m_read_meb if bh_meb_trig_mode != 0 */
355  /* NOTE: if trigger module is remote the complete (VSB) */
356  /* base address must be specified. example: */
357  /* f0580000 for a CAMAC trigger module in crate 2 */
358  /* serving m_read_meb running on an E7 in a VME */
359  /* crate. (see sketch at end of this file) */
360 /*---------------------------------------------------------------------------*/
361 INTU4 lp_cvc_irq; /* start address of the CVC irq physical segment */
362 INTU4 bl_cvc_irq_len; /* length of CVC irq phys. segment */
363 INTU4 bl_cvc_irq_source_off;/* offset from lp_cvc_irq to the CVC irq source register */
364 INTU4 bl_cvc_irq_mask_off; /* offset from lp_cvc_irq to the CVC irq mask register */
365 /*---------------------------------------------------------------------------*/
366 /* all values in this section will be initalized by a loader task */
367 INTS4 h_rd_tab_flg; /* -1 = init and readout tables invalid (this is set by */
368  /* the write_sbs_setup task */
369  /* 0 = init and readout tables have to be modified to */
370  /* virtual cnafs */
371  /* 1 = this modification is done and must not be done */
372  /* before a new table was loaded */
373 INTU4 bl_init_read_len; /* total length of init and readout CAMAC cnaf list for */
374  /* all crates and trigger types (in bytes) */
375 /* ------------------ end of fixed block --------------------------*/
376 /*---------------------------------------------------------------------------*/
377 INTU4 lp_rem_mem_base[SBS__N_CR];
378  /* physical base address for accessing slave crate memory */
379  /* seen from the MEB (pipes). This could be the VSB */
380  /* base address for accessing remote crates */
381 INTU4 bl_rem_mem_off[SBS__N_CR];
382  /* offset from lp_rem_mem_base[SBS__N_CR] to the memory */
383  /* space of the remote slaves (seen from MEB) */
384 INTU4 bl_rem_mem_len[SBS__N_CR];
385  /* lenght of the memory address window with the physical */
386  /* base adress lp_rem_mem_base[SBS__N_CR] */
387 /*---------------------------------------------------------------------------*/
388 INTU4 lp_rem_cam_base[SBS__N_CR];
389  /* physical base address for accessing slave directly via CAMAC */
390 INTU4 bl_rem_cam_off[SBS__N_CR];
391  /* offset from lp_rem_cam_base[SBS__N_CR] to the remote */
392  /* CAMAC space of the slaves (seen from MEB). */
393 INTU4 bl_rem_cam_len[SBS__N_CR];
394  /* lenght of the CAMAC address window with the physical */
395 /*---------------------------------------------------------------------------*/
396 INTU4 lp_loc_mem_base[SBS__N_CR];
397  /* base address for accessing local crate. (could be for */
398  /* example local CAMAC base or extended VME base.) */
399 INTU4 bl_loc_mem_len[SBS__N_CR];
400  /* length of physical segment for accessing local crate */
401  /* starting from lp_loc_mem_base[SBS__N_CR]. */
402 /*---------------------------------------------------------------------------*/
403 INTU4 l_loc_pipe_type[SBS__N_CR];
404  /* type of subevent pipe: 0: with smem_create */
405  /* 1: direct mapping */
406 INTU4 lp_loc_pipe_base[SBS__N_CR];
407  /* RAM start address of the crate controller (used for */
408  /* location of subevent pipe) */
409 INTU4 bl_pipe_off[SBS__N_CR];
410  /* offset from lp_ram_loc_start to start of the remote */
411  /* communication segment slave <-> master seen from the */
412  /* slave in bytes = start of subevent pipe */
413 INTU4 bl_pipe_seg_len[SBS__N_CR];
414  /* length of the remote communication segment in bytes */
415  /* = total lengt of subevent pipe */
416 INTU4 bl_pipe_len[SBS__N_CR]; /* number of subevent slots in a pipe */
417 INTU4 bh_controller_id[SBS__N_CR];
418  /* bh_controller_id MUST be set for ESONE CNAF execution */
419  /* 1 = CVC, 2 = E6, 3 = E7, 4 = AEB, 5 = CBV, 6 = CVI */
420  /* 7 = CAV (Q and X inverted) */
421 INTU4 bh_sy_asy_flg[SBS__N_CR];
422  /* indicates if this crate must be readout synchronous */
423  /* or asynchronous: 0 = synchronous, 1 = asynchronous */
424  /* this flag is only valid for crates with intelligent */
425  /* controller. At this point it is decided wether a crate */
426  /* is readout sync. or async. */
427 INTU4 bh_trig_stat_nr[SBS__N_CR];/* CAMAC station nr. of the trigger module, must be 1 */
428 INTU4 bl_trig_cvt[SBS__N_CR]; /* conversion time of trigger module */
429 INTU4 bl_trig_fct[SBS__N_CR]; /* fast clear acceptance time of trigger module */
430 INTS4 i_se_typ[SBS__N_CR]; /* subevent typ, default = 10 */
431 INTS4 i_se_subtyp[SBS__N_CR]; /* subevent subtyp: CAMAC = 1, FASTBUS = 2 */
432 INTS4 i_se_procid[SBS__N_CR]; /* subevent processor id */
433 /*---------------------------------------------------------------------------*/
434 INTU4 bh_rd_flg[SBS__N_CR];
435  /* 0 = crate not readout */
436  /* 1 = crate read out by meb */
437  /* 2 = crate readout by intelligent crate controller */
438 INTU4 bl_init_tab_off[SBS__N_CR];
439  /* offset from start of readout table segment to the */
440  /* start of the init table as a function of crate number */
441  /* (in longwords) */
442 INTU4 bi_init_tab_len[SBS__N_CR];
443  /* lenght of the init tables. if one of this values is 0 */
444  /* it means that this crate must not be not initalized */
445  /* (in longwords) */
447  /* maximal subevent length [b] of this crate and trigger */
449  /* offset from start of readout table segment to the */
450  /* start of the readout tables as a function of crate */
451  /* number and trigger type (in longwords) */
453  /* lenght of the readout tables. if one of this values */
454  /* is 0 it means that this crate for this trigger type is */
455  /* not read out (in longwords) */
456 /*---------------------------------------------------------------------------*/
458 
459 
460 /* JAM this is a helper structure to receive a setup structure originated by
461  * a 64 bit architecture mbs node. All addresses are long long*/
462 typedef struct
463 {
464 /*---------------------------------------------------------------------------*/
465 INTU4 l_endian; /* set to 1 */
466 INTU4 l_version; /* increment in f_ut_setup_ini after changes */
467 INTU4 bl_struc_len; /* sizeof(s_setup)/4 : length of this structure */
468 INTU4 l_fix_lw; /* (&lp_rem_mem_base-ps_setup)/4 : swapping size */
469 INTU4 bl_sbs__n_cr; /* set to SBS__N_CR */
470 INTU4 bl_sbs__n_trg_typ; /* set to SBS__N_TRG_TYP */
471 /*---------------------------------------------------------------------------*/
472 INTU4 bi_master; /* indicates type of master event builder */
473  /* meb: 1 = CVC, 2 = E6, 3 = E7 */
474 INTU4 bl_no_crates; /* Number of crates to read (bh_rd_flg > 0) */
475 INTU4 bh_crate_nr; /* crate nr. of readout processor: meb = 0, slave = 1-15 */
476  /* this value will be set by the load setup command and */
477  /* is not parsed from the .usf file */
478 /*---------------------------------------------------------------------------*/
479 INTU4 bl_ev_buf_len; /* length of single event buffer */
480 INTU4 bl_n_ev_buf; /* number of event buffers in a stream */
481 INTU4 bl_n_stream; /* number of streams */
482 /*---------------------------------------------------------------------------*/
483 INTU4 bi_evt_typ_sy; /* event type of synchronous events, default = 10 */
484 INTU4 bi_evt_typ_asy; /* event type of asynchronous events, default = 10 */
485 INTU4 bi_evt_subtyp_sy; /* event subtype of synchronous events, default = 1 */
486 INTU4 bi_evt_subtyp_asy; /* event subtype of asynchronous events, default = 2 */
487 INTS4 h_se_control; /* serves as branch identifier in a multi-branch system */
488 /*---------------------------------------------------------------------------*/
489 INTU4 bh_rd_typ; /* 0 = standard readout with readout tables */
490  /* 1 = user readout (function) */
491  /* if the following bh_meb_asy_flg is set to 1 there will be a second */
492  /* async. subevent pipe installed, which will be collected by the meb */
493  /* collector, but must be filled by a seperate process */
494 INTU4 bh_col_mode; /* indicates mode of this MEB collector or master readout:*/
495  /* 0 = standard, the collector formats events and passes */
496  /* the formatted event buffer streams to the */
497  /* transport */
498  /* 1 = collector collects subevents from the various */
499  /* SBS pipes, but no event formatting will be done. */
500  /* instead the collected subevents are written into a */
501  /* output pipe for the next layer node of the */
502  /* multi-branch multi-layer daq system. this mode */
503  /* requires bl_ml_pipe_base_addr, bl_ml_pipe_seg_len */
504  /* and bl_ml_pipe_len to be specified (see below). */
505  /* 2 = only m_read_meb and no collector runs on the */
506  /* SBS master (MEB). Its subevent pipe will be read */
507  /* by a node of the multi-branch multi-layer daq */
508  /* system. in this case the mb ml node gets the pipe */
509  /* specs from bl_pipe_seg_len and bl_pipe_len */
510  /* (see above). */
511  /* 3 = includes both 0 and 1 mode. */
512 /*---------------------------------------------------------------------------*/
513 ADDR64 bl_loc_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
514  /* window on the local crate JAM64*/
515 ADDR64 bl_rem_esone_base; /* base address to execute CAMAC cnafs via the ESONE */
516  /* window on the remote crate JAM64*/
517 INTU4 bl_esone_off; /* offset from standard to ESONE window in bytes */
518 INTU4 bl_cvc_crr_off; /* offset from to the CVC CAMAC Read Register */
519 INTU4 bl_cvc_csr_off; /* offset to the CVC Control and Status Register */
520 INTU4 bl_cvc_clb_off; /* offset to the CVC CAMAC Lam Buffer */
521 INTU4 bl_se_meb_asy_len; /* length of the async. pipe of the master, including */
522  /* control and data */
523 INTU4 bh_meb_asy_flg; /* indicates if meb must collect must an async. pipe */
524  /* residing on the meb: 0 = no, 1 = yes */
525 
526 ADDR64 bl_ml_pipe_base_addr;/* base address of the multi-branch multi-layer daq JAM64 */
527  /* system output pipe. */
528  /* only requested ig bh_col_mode = 1,2 */
529 
530 ADDR64 bl_ml_pipe_seg_len; /* length of the multi-branch multi-layer daq system JAM64 */
531  /* output pipe. (total lengt of subevent pipe) */
532  /* only requested ig bh_col_mode = 1,2 */
533 
534 INTU4 bl_ml_pipe_len; /* number of subevent/fragment slots in the multi-branch */
535  /* multi-layer daq system output pipe */
536  /* only requested ig bh_col_mode = 1,2 */
537 INTU4 bl_n_col_retry; /* number of retries the subevent collect process makes */
538  /* until giving up time slice */
539 /*---------------------------------------------------------------------------*/
540 INTU4 bh_meb_trig_mode; /* if this is set to NON zero a special mode is requested */
541  /* for the trigger module serving m_read_meb. */
542  /* this could be: */
543  /* NOT irq (LAM, VME irq) */
544  /* or NOT standard base address (VME) */
545  /* or NOT local crate */
546  /* if bh_meb_trig_mode is NOT 0 always the following two */
547  /* setup paramters will be taken for type and base addr. */
548  /* */
549  /* NOTE: the fast clear and conversion time will be taken */
550  /* from bl_trig_fct[0] and bl_trig_cvt[0] from this */
551  /* setup structure */
552  /* */
553  /* 0 = standard = local interrupt (CAMAC LAM, VME IRQ) */
554  /* 1 = special: local interrupt (CAMAC LAM, VME IRQ) */
555  /* 2 = special: remote VSB interrupt (not yet impleme) */
556  /* 3 = special: polling */
558  /* 1 = CAMAC type trigger module */
559  /* 2 = VME type trigger module */
560  /* 3 = FASTBUS type triggermodule */
561 
563  /* base address of trigger module acting together with */
564  /* m_read_meb if bh_meb_trig_mode != 0 */
565  /* NOTE: if trigger module is remote the complete (VSB) */
566  /* base address must be specified. example: */
567  /* f0580000 for a CAMAC trigger module in crate 2 */
568  /* serving m_read_meb running on an E7 in a VME */
569  /* crate. (see sketch at end of this file)
570  * JAM64 changed type to ADDRS*/
571 
572 
573 /*---------------------------------------------------------------------------*/
574 INTU4 lp_cvc_irq; /* start address of the CVC irq physical segment */
575 INTU4 bl_cvc_irq_len; /* length of CVC irq phys. segment */
576 INTU4 bl_cvc_irq_source_off;/* offset from lp_cvc_irq to the CVC irq source register */
577 INTU4 bl_cvc_irq_mask_off; /* offset from lp_cvc_irq to the CVC irq mask register */
578 /*---------------------------------------------------------------------------*/
579 /* all values in this section will be initalized by a loader task */
580 INTS4 h_rd_tab_flg; /* -1 = init and readout tables invalid (this is set by */
581  /* the write_sbs_setup task */
582  /* 0 = init and readout tables have to be modified to */
583  /* virtual cnafs */
584  /* 1 = this modification is done and must not be done */
585  /* before a new table was loaded */
586 INTU4 bl_init_read_len; /* total length of init and readout CAMAC cnaf list for */
587  /* all crates and trigger types (in bytes) */
588 /* ------------------ end of fixed block --------------------------*/
589 
591 
592 
593 
594 
595 
596 
597 /*
598 * address offset for memory access from the master event builder to the slave
599 * CVC's via VSB. these offsets point to the memory address 0x100000 seen
600 * from the slave CVC, which is the beginning of the RAM of the CVC. only
601 * longword access possible, the following offsets are given in bytes.
602 *
603 * in the case of accessing non local crates by CAMAC cnaf's via VSB, the
604 * shown address offset (CAM_CRT_OFF) between two consecutive crates is
605 * automatically included by crate number contained in the cnaf. the effective
606 * physical offset to the cnafs is 0x08180000
607 */
608 /*----------------------------------------------------------------------------!
609 ! VSB and CAMAC memory on the CVC slaves, seen from the MEB CVC !
610 ! !
611 ! !
612 ! 0x8000000 0x8200000 0x8400000 !
613 ! | | | !
614 ! | | | !
615 ! | VSB_CRT_OFF | VSB_CRT_OFF | !
616 ! V S B |===================|===================|===... !
617 ! | 0x200000 | 0x200000 | !
618 ! | | | !
619 ! | crate|1 crate|2 !
620 ! | | | !
621 ! VSB_CAM_START | (VSB_OFF = 0x0) !
622 !==============>| !
623 ! 0x8000000 | | | !
624 ! | crate|1 crate|2 !
625 ! | | | !
626 ! | CAM_OFF | CAM_CRT_OFF | CAM_CRT_OFF | !
627 ! C A M A C |================|===================|===================|==..!
628 ! | 0x180000 | 0x200000 | 0x200000 | !
629 ! | | | | !
630 ! | | | | !
631 ! 0x8000000 0x8180000 0x8380000 0x8580000 !
632 !----------------------------------------------------------------------------*/
633 
634 #endif
INTU4 bh_crate_nr
Definition: s_setup.h:51
INTU4 bl_n_col_retry
Definition: s_setup.h:537
INTU4 bl_sbs__n_trg_typ
Definition: s_setup.h:470
INTU4 bh_special_meb_trig_type
Definition: s_setup.h:557
INTU4 bl_cvc_crr_off
Definition: s_setup.h:94
INTU4 bl_se_meb_asy_len
Definition: s_setup.h:521
INTU4 l_fix_lw
Definition: s_setup.h:44
INTU4 bl_rem_esone_base
Definition: s_setup.h:309
INTU4 bi_master
Definition: s_setup.h:48
INTU4 bi_evt_subtyp_asy
Definition: s_setup.h:486
ADDRS bl_special_meb_trig_base
Definition: s_setup.h:138
#define SBS__N_TRG_TYP
Definition: sbs_def.h:28
INTU4 bl_sbs__n_trg_typ
Definition: s_setup.h:264
INTU4 bl_special_meb_trig_base
Definition: s_setup.h:352
INTU4 bl_no_crates
Definition: s_setup.h:50
INTU4 bi_evt_subtyp_asy
Definition: s_setup.h:62
INTU4 bh_meb_asy_flg
Definition: s_setup.h:523
INTU4 bl_ml_pipe_len
Definition: s_setup.h:534
INTU4 bh_meb_trig_mode
Definition: s_setup.h:116
INTU4 bl_se_meb_asy_len
Definition: s_setup.h:315
INTU4 bl_init_read_len
Definition: s_setup.h:373
INTU4 bl_cvc_irq_source_off
Definition: s_setup.h:363
INTU4 bh_col_mode
Definition: s_setup.h:70
INTU4 bl_n_ev_buf
Definition: s_setup.h:56
INTU4 bh_meb_asy_flg
Definition: s_setup.h:99
INTU4 bl_ml_pipe_seg_len
Definition: s_setup.h:322
INTU4 bl_se_meb_asy_len
Definition: s_setup.h:97
INTS4 h_rd_tab_flg
Definition: s_setup.h:156
INTU4 bl_cvc_irq_mask_off
Definition: s_setup.h:364
INTU4 bl_cvc_csr_off
Definition: s_setup.h:95
ADDRS bl_ml_pipe_seg_len
Definition: s_setup.h:106
INTU4 bl_cvc_irq_len
Definition: s_setup.h:575
INTU4 bh_meb_trig_mode
Definition: s_setup.h:540
INTU4 bi_evt_typ_asy
Definition: s_setup.h:484
INTU4 bl_ml_pipe_len
Definition: s_setup.h:110
unsigned int INTU4
Definition: typedefs.h:29
INTU4 bl_n_col_retry
Definition: s_setup.h:328
INTU4 bl_esone_off
Definition: s_setup.h:93
int INTS4
Definition: typedefs.h:28
INTU4 bl_ml_pipe_len
Definition: s_setup.h:325
INTU4 bl_struc_len
Definition: s_setup.h:43
INTU4 bl_cvc_clb_off
Definition: s_setup.h:520
INTU4 bl_ml_pipe_base_addr
Definition: s_setup.h:319
INTU4 bl_cvc_csr_off
Definition: s_setup.h:519
INTU4 bi_evt_typ_asy
Definition: s_setup.h:60
INTU4 bl_cvc_irq_mask_off
Definition: s_setup.h:153
INTU4 bl_n_stream
Definition: s_setup.h:57
ADDR64 bl_ml_pipe_base_addr
Definition: s_setup.h:526
#define SBS__N_CR
Definition: sbs_def.h:27
INTU4 bh_special_meb_trig_type
Definition: s_setup.h:348
ADDRS bl_ml_pipe_base_addr
Definition: s_setup.h:102
INTU4 bl_n_col_retry
Definition: s_setup.h:113
INTU4 bl_cvc_irq_len
Definition: s_setup.h:362
INTU4 bl_cvc_irq_source_off
Definition: s_setup.h:152
INTU4 bl_loc_esone_base
Definition: s_setup.h:307
INTU4 bl_init_read_len
Definition: s_setup.h:586
INTU4 l_version
Definition: s_setup.h:42
INTU4 bl_sbs__n_trg_typ
Definition: s_setup.h:46
INTU4 bi_evt_subtyp_asy
Definition: s_setup.h:280
INTU4 bl_cvc_clb_off
Definition: s_setup.h:96
INTU4 bi_evt_subtyp_sy
Definition: s_setup.h:279
INTU4 bi_evt_subtyp_sy
Definition: s_setup.h:61
INTU4 bl_ev_buf_len
Definition: s_setup.h:55
INTU4 bh_meb_trig_mode
Definition: s_setup.h:331
ADDRS bl_loc_esone_base
Definition: s_setup.h:89
INTU4 bi_evt_subtyp_sy
Definition: s_setup.h:485
INTU4 bi_evt_typ_sy
Definition: s_setup.h:59
INTU4 bi_evt_typ_asy
Definition: s_setup.h:278
INTS4 h_se_control
Definition: s_setup.h:63
INTU4 bh_meb_asy_flg
Definition: s_setup.h:317
INTU4 bl_cvc_irq_len
Definition: s_setup.h:151
ADDR64 bl_rem_esone_base
Definition: s_setup.h:515
INTU4 l_endian
Definition: s_setup.h:41
INTU4 bl_cvc_clb_off
Definition: s_setup.h:314
INTU4 lp_cvc_irq
Definition: s_setup.h:150
INTU4 bl_cvc_crr_off
Definition: s_setup.h:518
INTU4 bl_cvc_crr_off
Definition: s_setup.h:312
ADDR64 bl_loc_esone_base
Definition: s_setup.h:513
INTU4 bl_init_read_len
Definition: s_setup.h:162
INTU4 bl_sbs__n_cr
Definition: s_setup.h:45
ADDRS bl_rem_esone_base
Definition: s_setup.h:91
INTU4 bl_cvc_csr_off
Definition: s_setup.h:313
ADDR64 bl_ml_pipe_seg_len
Definition: s_setup.h:530
INTU4 bl_cvc_irq_mask_off
Definition: s_setup.h:577
INTU4 bh_rd_typ
Definition: s_setup.h:65
ADDR64 bl_special_meb_trig_base
Definition: s_setup.h:562
INTU4 bl_cvc_irq_source_off
Definition: s_setup.h:576
INTU4 bh_special_meb_trig_type
Definition: s_setup.h:133