36#define VERSION__DAQST 63
37#define VERSION__SETUP 63
38#define VERSION__SET_ML 63
39#define VERSION__SET_MO 63
69 if(ps_daqst == NULL)
return -1;
74 ps_daqst->
l_fix_lw = ((ADDRS)&ps_daqst->
c_pname[0][0]-(ADDRS)ps_daqst)/4;
152 INTS4 l_swap=0, len_64, n_trg, max_proc;
157 memset((
void *)ps_daqst,0,
sizeof(
s_daqst));
161 if(ps_daqst->
l_endian != 1) l_swap = 1;
181 ps_daqst->
l_fix_lw += n_trg*3 + 212 + len_64/4*3;
228if(ps_setup == NULL)
return -1;
271 if(ps_setup == NULL || src == NULL)
return -1;
344 if(ps_setup == NULL || src == NULL)
return -1;
419INTU4 *pl_count,*pl_size;
511INTS4 i,k,l_items,l_size,l_crate;
517 memset(ps_setup,0,
sizeof(
s_setup));
521if(ps_setup->
l_endian != 1) l_swap = 1;
534 if (ps_setup_32 == NULL) {
535 printf (
"f_ut_setup_r memory allocation error");
553 if (ps_setup_64 == NULL) {
554 printf (
"f_ut_setup_r memory allocation error");
571 printf(
"f_ut_setup_r finds non consistent l_fix_lw=%d. do not read further!", ps_setup->
l_fix_lw);
578pl_b = (
INTU4 *) malloc(l_size * l_items * 4);
583for(i=0;i<l_items;i++)
603 ps_setup->
i_se_typ[l_crate] = *pl_o++;
647if(ps_set_ml == NULL)
return -1;
690INTU4 *pl_count,*pl_s;
702 for(k=0;k<ps_set_ml->
l_short_len/4;k++)*pl_o++ = *pl_s++;
704 for(k=0;k<ps_set_ml->
l_long_len/4;k++)*pl_o++ = *pl_s++;
750if(ps_set_ml->
l_endian != 1) l_swap = 1;
792if(ps_set_mo == NULL)
return -1;
869if(ps_set_mo->
l_endian != 1) l_swap=1;
INTS4 f_stc_write(void *p_buffer, INTS4 i_buflen, INTS4 i_channel)
INTS4 f_stc_read(void *p_buffer, INTS4 i_buflen, INTS4 i_channel, INTS4 i_timeout)
int f_swaplw(int *pp_source, int l_len, int *pp_dest)
INTS4 f_ut_setup_r(s_setup *ps_setup, INTS4 l_tcp)
INTS4 f_ut_set_mo(s_set_mo *ps_set_mo, INTS4 l_tcp)
INTS4 f_ut_set_ml_ini(s_set_ml *ps_set_ml)
INTS4 f_ut_set_mo_ini(s_set_mo *ps_set_mo)
INTS4 f_ut_setup_copy64(s_setup *ps_setup, s_setup_64_receiver *src)
INTS4 f_ut_setup(s_setup *ps_setup, INTU4 *pl_o, INTS4 l_tcp)
INTS4 f_ut_status_ini(s_daqst *ps_daqst)
INTS4 f_ut_status(s_daqst *ps_daqst, INTS4 l_tcp)
INTS4 f_ut_set_mo_r(s_set_mo *ps_set_mo, INTS4 l_tcp)
INTS4 f_ut_setup_ini(s_setup *ps_setup)
INTS4 f_ut_setup_copy32(s_setup *ps_setup, s_setup_32_receiver *src)
INTS4 f_ut_status_r(s_daqst *ps_daqst, INTS4 l_tcp)
INTS4 f_ut_set_ml_r(s_set_ml *ps_set_ml, INTS4 l_tcp)
INTS4 f_ut_set_ml(s_set_ml *ps_set_ml, INTU4 *pl_o, INTS4 l_tcp)
INTU4 bh_running[SYS__N_MAX_PROCS]
CHARS c_out_chan[SBS__STR_LEN_64]
CHARS c_pname[SYS__N_MAX_PROCS][SBS__STR_LEN_64]
CHARS c_user[SBS__STR_LEN_64]
INTU4 bh_daqst_initalized
CHARS c_sbs_setup_path[ML__N_RD_PIPE][128]
CHARS c_rd_hostname[ML__N_RD_PIPE][16]
CHARS c_ds_hostname[MO__N_NODE][16]
CHARS c_dr_hostname[MO__N_NODE][16]
INTU4 bl_special_meb_trig_base
INTU4 bh_special_meb_trig_type
INTU4 bl_cvc_irq_mask_off
INTU4 bl_ml_pipe_base_addr
INTU4 bl_cvc_irq_source_off
ADDR64 bl_ml_pipe_seg_len
INTU4 bh_special_meb_trig_type
INTU4 bl_cvc_irq_source_off
ADDR64 bl_special_meb_trig_base
INTU4 bl_cvc_irq_mask_off
ADDR64 bl_ml_pipe_base_addr
INTU4 bl_max_se_len[SBS__N_CR][SBS__N_TRG_TYP]
ADDRS lp_loc_mem_base[SBS__N_CR]
ADDRS bl_special_meb_trig_base
ADDRS bl_ml_pipe_base_addr
INTS4 i_se_typ[SBS__N_CR]
INTU4 bl_cvc_irq_source_off
INTU4 bl_pipe_len[SBS__N_CR]
INTU4 bi_init_tab_len[SBS__N_CR]
INTU4 bl_rd_tab_off[SBS__N_CR][SBS__N_TRG_TYP]
INTU4 bl_trig_fct[SBS__N_CR]
INTS4 i_se_subtyp[SBS__N_CR]
INTU4 bh_controller_id[SBS__N_CR]
INTU4 bh_special_meb_trig_type
INTU4 bl_trig_cvt[SBS__N_CR]
ADDRS lp_loc_pipe_base[SBS__N_CR]
INTU4 bl_init_tab_off[SBS__N_CR]
ADDRS lp_rem_mem_base[SBS__N_CR]
ADDRS lp_rem_cam_base[SBS__N_CR]
INTS4 i_se_procid[SBS__N_CR]
INTU4 bl_rem_cam_len[SBS__N_CR]
INTU4 bi_rd_tab_len[SBS__N_CR][SBS__N_TRG_TYP]
ADDRS bl_loc_mem_len[SBS__N_CR]
INTU4 bh_rd_flg[SBS__N_CR]
ADDRS bl_rem_mem_len[SBS__N_CR]
INTU4 bl_cvc_irq_mask_off
ADDRS bl_pipe_off[SBS__N_CR]
ADDRS bl_rem_mem_off[SBS__N_CR]
ADDRS bl_rem_cam_off[SBS__N_CR]
INTU4 bh_sy_asy_flg[SBS__N_CR]
ADDRS bl_pipe_seg_len[SBS__N_CR]
INTU4 bh_trig_stat_nr[SBS__N_CR]