0000000000000000000000000000000000000000 6c1b452057f5766f5d90bc9649abf38202a06828 Bastian Löher <b.loeher@gsi.de> 1678266537 +0100	branch: Created from refs/remotes/origin/bl
6c1b452057f5766f5d90bc9649abf38202a06828 01dfa33824382a8eee9fbebac0c22131203face3 Bastian Löher <b.loeher@gsi.de> 1678266640 +0100	commit: Disable polarity switch. Tested to be OK.
01dfa33824382a8eee9fbebac0c22131203face3 70650b7fe46e882ce992ff30c3e9612460649e32 Bastian Löher <b.loeher@gsi.de> 1678266665 +0100	commit: Send rataclock on ECL output.
70650b7fe46e882ce992ff30c3e9612460649e32 6b71a26aff5f8db3e98d71fe5b1f013a3470b681 Bastian Löher <b.loeher@gsi.de> 1678266688 +0100	commit: Add UART output module.
6b71a26aff5f8db3e98d71fe5b1f013a3470b681 6d92d3a4af019e9915437b373be2dba15fdaa292 Bastian Löher <b.loeher@gsi.de> 1678314074 +0100	commit: Remove polarity selection for butis input.
6d92d3a4af019e9915437b373be2dba15fdaa292 464190cf07a0ca8643ce43b512fb29f4ffd00b88 Bastian Löher <b.loeher@gsi.de> 1678314178 +0100	commit: Add UART TX on res 7 (now an output). Polarity selection was removed. All other res inputs are shifted down by 1.
464190cf07a0ca8643ce43b512fb29f4ffd00b88 a4c66569c97d71993d1a01db5fa7b3ace09e8356 Bastian Löher <b.loeher@gsi.de> 1678351522 +0100	commit: Remove unused code.
a4c66569c97d71993d1a01db5fa7b3ace09e8356 75e10d9f651a25280c62a7d133a3eacaafffe9b1 Bastian Löher <b.loeher@gsi.de> 1678357055 +0100	commit: Remove some dead code. Heavily pipeline fast signals going to ODDR outputs.
75e10d9f651a25280c62a7d133a3eacaafffe9b1 65a41c4efa522b8b4904663c6640746f08723325 Bastian Löher <b.loeher@gsi.de> 1678358664 +0100	commit: Enable rataclock receiver again. Rename some signals to be more consistent.
65a41c4efa522b8b4904663c6640746f08723325 9d6b0a4d1f1d785bfe03a0fef72eaf40599956f2 Bastian Löher <b.loeher@gsi.de> 1678372100 +0100	commit: Fix timing violations.
9d6b0a4d1f1d785bfe03a0fef72eaf40599956f2 95c4aba3e7358a173db124db4808e3f979a9b585 Bastian Löher <b.loeher@gsi.de> 1678377130 +0100	commit: Enable ratatime sender, run sync_lost pipeline on clk_125 instead of clk_125_rata.
95c4aba3e7358a173db124db4808e3f979a9b585 4e330a3d55b3675b7ba84479b20468fb18072d39 Bastian Löher <b.loeher@gsi.de> 1678442496 +0100	commit: Add one pipeline stage for sync_status sync_lost.
4e330a3d55b3675b7ba84479b20468fb18072d39 3fb1eee39fcc6aebbb24ffe89d69599ba2c03ce3 Bastian Löher <b.loeher@gsi.de> 1678456878 +0100	commit: Generate 90 degree phase shifted clock from separate PLL after clock multiplexer to improve timing. Some whitespace.
