| clk_wiz_v3_6 Project Status (03/11/2013 - 18:04:06) | |||
| Project File: | fx2lp_loopback_proj.xise | Parser Errors: | No Errors |
| Module Name: | fifo_512x8 | Implementation State: | Programming File Not Generated |
| Target Device: | xc6slx25-3ftg256 |
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| Product Version: | ISE 14.4 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Current | Mon Mar 11 18:04:00 2013 | |
| WebTalk Log File | Current | Mon Mar 11 18:04:05 2013 | |