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PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
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PROP_PropSpecInProjFile=Store all values |
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PROP_SynthTopFile=changed |
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PROP_UseSmartGuide=false |
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PROP_intProjectCreationTimestamp=2013-03-11T11:18:09 |
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PROP_intWbtProjectIteration=14 |
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PROP_DevFamilyPMName=spartan6 |
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PROP_Synthesis_Tool=XST (VHDL/Verilog) |
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PROP_PreferredLanguage=VHDL |
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FILE_VHDL=3 |