Timing Constraints - Mi. Feb 8 11:48:13 2023
| Met | Constraint | Check | Worst Case Slack | Best Case Achievable | Timing Errors | Timing Score |
| No | TS_clock_generators_clocks_rataclock_clkout0 = PERIOD TIMEGRP "clock_generators_clocks_rataclock_clkout0" TS_lemo_input_0_ / 5 HIGH 50% | SETUP HOLD | 0.369ns -5.120ns | 7.267ns | 0 1 | 0 5120 |
| No | TS_clk_200_int_0 = PERIOD TIMEGRP "clk_200_int_0" TS_CK_125N_IN / 1.6 HIGH 50% | SETUP HOLD | -0.787ns 0.388ns | 6.574ns | 1 0 | 787 0 |
| Yes | TS_clk_125_butis = PERIOD TIMEGRP "clk_125_butis" TS_any_input_0_ / 0.625 HIGH 50% | SETUP HOLD | 0.312ns 1.059ns | 4.104ns | 0 0 | 0 0 |
| Yes | NET "io_buffers/lemo_in[0].input_buffer" MAXSKEW = 1.5 ns | NETSKEW | 0.416ns | 1.084ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_butis_clkout0 = PERIOD TIMEGRP "clock_generators_clocks_butis_clkout0" TS_any_input_0_ HIGH 50% | SETUP HOLD | 0.570ns 0.385ns | 4.430ns | 0 0 | 0 0 |
| Yes | TS_clock_generators_clocks_clkout1_0 = PERIOD TIMEGRP "clock_generators_clocks_clkout1_0" TS_CK_125N_IN / 0.8 HIGH 50% | SETUP HOLD | 0.653ns 0.370ns | 9.347ns | 0 0 | 0 0 |
| Yes | TS_any_input_0_ = PERIOD TIMEGRP "any_input<0>" 5 ns HIGH 50% | MINLOWPULSE | 2.200ns | 2.800ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_clkout0_0 = PERIOD TIMEGRP "clock_generators_clocks_clkout0_0" TS_CK_125N_IN HIGH 50% | SETUP HOLD MINPERIOD | 2.492ns 1.449ns 6.270ns | -0.492ns 1.730ns | 0 0 0 | 0 0 0 |
| Yes | TS_clk_200_int = PERIOD TIMEGRP "clk_200_int" ts_ck_125p_in / 1.6 HIGH 50% | MINPERIOD | 3.361ns | 1.639ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_rataclock_clkout1 = PERIOD TIMEGRP "clock_generators_clocks_rataclock_clkout1" TS_lemo_input_0_ / 5 PHASE 2 ns HIGH 50% | SETUP HOLD | 4.105ns 2.249ns | 2.526ns | 0 0 | 0 0 |
| Yes | TS_CK_125N_IN = PERIOD TIMEGRP "CK_125N_IN" 8 ns HIGH 50% | MINLOWPULSE | 4.666ns | 3.334ns | 0 | 0 |
| Yes | ts_ck_125p_in = PERIOD TIMEGRP "tnm_ck_125" 8 ns HIGH 50% | MINLOWPULSE | 4.666ns | 3.334ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_clkout0 = PERIOD TIMEGRP "clock_generators_clocks_clkout0" ts_ck_125p_in HIGH 50% | MINPERIOD | 6.270ns | 1.730ns | 0 | 0 |
| Yes | TS_lemo_input_0_ = PERIOD TIMEGRP "lemo_input<0>" 40 ns HIGH 50% | MINLOWPULSE | 30.000ns | 10.000ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_clkout1 = PERIOD TIMEGRP "clock_generators_clocks_clkout1" ts_ck_125p_in / 0.8 HIGH 50% | MINPERIOD | 8.270ns | 1.730ns | 0 | 0 |
| Yes | TS_send_clock_i_transmit = PERIOD TIMEGRP "send_clock/i_transmit" 40 ns HIGH 50% | MINPERIOD | 38.361ns | 1.639ns | 0 | 0 |
| Yes | TS_clock_generators_clocks_butis_clkout2 = PERIOD TIMEGRP "clock_generators_clocks_butis_clkout2" TS_any_input_0_ / 0.05 HIGH 50% | SETUP HOLD | 97.967ns 0.502ns | 2.033ns | 0 0 | 0 0 |