fx2lp_slaveFIFO2b_loopback_fpga_top Project Status (12/03/2021 - 17:57:08)
Project File: fx2lp_loopback.xise Parser Errors: No Errors
Module Name: fx2lp_slaveFIFO2b_loopback_fpga_top Implementation State: Programming File Generated
Target Device: xc6slx150t-3csg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
11 Warnings (5 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 44 184,304 1%  
    Number used as Flip Flops 44      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 82 92,152 1%  
    Number used as logic 82 92,152 1%  
        Number using O6 output only 61      
        Number using O5 output only 0      
        Number using O5 and O6 21      
        Number used as ROM 0      
    Number used as Memory 0 21,680 0%  
Number of occupied Slices 29 23,038 1%  
Number of MUXCYs used 24 46,076 1%  
Number of LUT Flip Flop pairs used 82      
    Number with an unused Flip Flop 39 82 47%  
    Number with an unused LUT 0 82 0%  
    Number of fully used LUT-FF pairs 43 82 52%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
4 184,304 1%  
Number of bonded IOBs 22 296 7%  
    Number of LOCed IOBs 20 22 90%  
    IOB Flip Flops 3      
Number of RAMB16BWERs 0 268 0%  
Number of RAMB8BWERs 1 536 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 12 0%  
Number of ILOGIC2/ISERDES2s 0 586 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 586 0%  
Number of OLOGIC2/OSERDES2s 3 586 1%  
    Number used as OLOGIC2s 3      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of GTPA1_DUALs 0 2 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 6 16%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.02      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 3. Dez 17:56:15 202105 Warnings (5 new)5 Infos (5 new)
Translation ReportCurrentFr 3. Dez 17:56:23 2021002 Infos (0 new)
Map ReportCurrentFr 3. Dez 17:56:39 202101 Warning (0 new)9 Infos (1 new)
Place and Route ReportCurrentFr 3. Dez 17:56:57 202104 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentFr 3. Dez 17:57:04 2021003 Infos (0 new)
Bitgen ReportCurrentFr 3. Dez 17:58:25 202101 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateDi 26. Mrz 02:05:56 2013
WebTalk Log FileCurrentFr 3. Dez 17:58:26 2021

Date Generated: 12/09/2021 - 11:12:06