| Project Statistics |
| PROPEXT_MapGlobalOptimization_spartan6=Speed |
PROP_Enable_Message_Filtering=false |
| PROP_FitterReportFormat=HTML |
PROP_ImpactProjectFile=changed |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_MapLogicOptimization_spartan6=true |
| PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
| PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
| PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=J:/Xilinx/14.7/ISE_DS/ISE/data/default.xds |
| PROP_UserConstraintEditorPreference=Text Editor |
PROP_UserEditorCustomSetting=gvim $1 |
| PROP_UserEditorPreference=Custom |
PROP_intProjectCreationTimestamp=2021-12-03T16:23:09 |
| PROP_intWbtProjectID=4962CFB31F7F426AB9AA0D83B02EEFBD |
PROP_intWbtProjectIteration=136 |
| PROP_intWorkingDirLocWRTProjDir=UnderProjDir |
PROP_intWorkingDirUsed=Yes |
| PROP_xilxBitgCfg_GenOpt_Compress=true |
PROP_xilxBitgCfg_Rate_spartan6=26 |
| PROP_xilxMapAllowLogicOpt=true |
PROP_AutoTop=true |
| PROP_DevFamily=Spartan6 |
PROP_MapRegDuplication_spartan6=On |
| PROP_xilxBitgCfg_GenOpt_BinaryFile=true |
PROP_xilxMapEnableMultiThreading=2 |
| PROP_DevDevice=xc6slx150t |
PROP_DevFamilyPMName=spartan6 |
| PROP_DevPackage=csg484 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
| PROP_parEnableMultiThreading_spartan6=4 |
PROP_DevSpeed=-3 |
| PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
| FILE_VERILOG=1 |
FILE_VHDL=56 |