DTL-STS tests database

FEB_2528 02.06.26 13:28:40

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-031-010-027-06
...SMX_1.root
link: XA-000-09-004-031-008-006-02
...SMX_3.root
link: XA-000-09-004-031-005-004-05
...SMX_5.root
link: XA-000-09-004-031-008-004-02
...SMX_7.root
link: XA-000-09-004-031-008-004-02
...VddmCSAstatus.root
Info
            13:28:40:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:28:40:ST3_Shared:INFO:	                       FEB-Microcable                       
13:28:40:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:28:40:febtest:INFO:	Testing FEB with SN 2528
==============================================OOO==============================================
13:28:41:smx_tester:INFO:	Scanning setup
13:28:41:elinks:INFO:	Disabling clock on downlink 0
13:28:41:elinks:INFO:	Disabling clock on downlink 1
13:28:41:elinks:INFO:	Disabling clock on downlink 2
13:28:41:elinks:INFO:	Disabling clock on downlink 3
13:28:41:elinks:INFO:	Disabling clock on downlink 4
13:28:41:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:28:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:28:41:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:28:41:elinks:INFO:	Disabling clock on downlink 0
13:28:41:elinks:INFO:	Disabling clock on downlink 1
13:28:42:elinks:INFO:	Disabling clock on downlink 2
13:28:42:elinks:INFO:	Disabling clock on downlink 3
13:28:42:elinks:INFO:	Disabling clock on downlink 4
13:28:42:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:28:42:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:28:42:elinks:INFO:	Disabling clock on downlink 0
13:28:42:elinks:INFO:	Disabling clock on downlink 1
13:28:42:elinks:INFO:	Disabling clock on downlink 2
13:28:42:elinks:INFO:	Disabling clock on downlink 3
13:28:42:elinks:INFO:	Disabling clock on downlink 4
13:28:42:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
13:28:42:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
13:28:42:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:28:42:elinks:INFO:	Disabling clock on downlink 0
13:28:42:elinks:INFO:	Disabling clock on downlink 1
13:28:42:elinks:INFO:	Disabling clock on downlink 2
13:28:42:elinks:INFO:	Disabling clock on downlink 3
13:28:42:elinks:INFO:	Disabling clock on downlink 4
13:28:42:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:28:42:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:28:42:elinks:INFO:	Disabling clock on downlink 0
13:28:42:elinks:INFO:	Disabling clock on downlink 1
13:28:42:elinks:INFO:	Disabling clock on downlink 2
13:28:42:elinks:INFO:	Disabling clock on downlink 3
13:28:42:elinks:INFO:	Disabling clock on downlink 4
13:28:42:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:28:42:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
13:28:42:setup_element:INFO:	Scanning clock phase
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:28:42:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:28:42:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
13:28:42:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
13:28:42:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
13:28:42:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:28:42:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
13:28:42:setup_element:INFO:	Scanning data phases
13:28:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:28:43:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:28:48:setup_element:INFO:	Data phase scan results for group 0, downlink 2
13:28:48:setup_element:INFO:	Eye window for uplink 24: ______________XXXXXX____________________
Data delay found: 36
13:28:48:setup_element:INFO:	Eye window for uplink 25: ________________XXXXX___________________
Data delay found: 38
13:28:48:setup_element:INFO:	Eye window for uplink 26: _________________XXXXXXX________________
Data delay found: 0
13:28:48:setup_element:INFO:	Eye window for uplink 27: ___________________XXXXXX_______________
Data delay found: 1
13:28:48:setup_element:INFO:	Eye window for uplink 28: _________________XXXXXX_________________
Data delay found: 39
13:28:48:setup_element:INFO:	Eye window for uplink 29: _________________XXXXX__________________
Data delay found: 39
13:28:48:setup_element:INFO:	Eye window for uplink 30: ____________________XXXXXX______________
Data delay found: 2
13:28:48:setup_element:INFO:	Eye window for uplink 31: __________________XXXXXXX_______________
Data delay found: 1
13:28:48:setup_element:INFO:	Setting the data phase to 36 for uplink 24
13:28:48:setup_element:INFO:	Setting the data phase to 38 for uplink 25
13:28:48:setup_element:INFO:	Setting the data phase to 0 for uplink 26
13:28:48:setup_element:INFO:	Setting the data phase to 1 for uplink 27
13:28:48:setup_element:INFO:	Setting the data phase to 39 for uplink 28
13:28:48:setup_element:INFO:	Setting the data phase to 39 for uplink 29
13:28:48:setup_element:INFO:	Setting the data phase to 2 for uplink 30
13:28:48:setup_element:INFO:	Setting the data phase to 1 for uplink 31
==============================================OOO==============================================
13:28:48:setup_element:INFO:	Beginning SMX ASICs map scan
13:28:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:28:48:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:28:48:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:28:48:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
13:28:48:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
13:28:48:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:28:48:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:28:48:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:28:48:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:28:49:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:28:49:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:28:49:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:28:49:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:28:50:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ____________________________________________________________________XXXXXXXXX___
      Uplink 25: ____________________________________________________________________XXXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXX___
      Uplink 27: _____________________________________________________________________XXXXXXXX___
      Uplink 28: ___________________________________________________________________XXXXXXXXX____
      Uplink 29: ___________________________________________________________________XXXXXXXXX____
      Uplink 30: _____________________________________________________________________XXXXXXXX___
      Uplink 31: _____________________________________________________________________XXXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 36
      Window Length: 34
      Eye Window: ______________XXXXXX____________________
    Uplink 25:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 26:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________
    Uplink 27:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 29:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 30:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 33
      Eye Window: __________________XXXXXXX_______________

==============================================OOO==============================================
13:28:50:setup_element:INFO:	Performing Elink synchronization
13:28:50:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:28:50:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:28:50:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:28:50:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
13:28:50:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
13:28:50:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
13:28:51:febtest:INFO:	Init all SMX (CSA): 30
13:28:59:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:28:59:febtest:INFO:	30-01 | XA-000-09-004-031-010-027-06 |  47.3 | 1118.1
13:28:59:febtest:INFO:	28-03 | XA-000-09-004-031-008-006-02 |  15.6 | 1206.9
13:28:59:febtest:INFO:	26-05 | XA-000-09-004-031-005-004-05 |  34.6 | 1153.7
13:28:59:febtest:INFO:	24-07 | XA-000-09-004-031-008-004-02 |  28.2 | 1183.3
13:29:00:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
13:29:02:ST3_smx:INFO:	chip: 30-1 	 47.250730 C 	 1129.995435 mV
13:29:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:03:ST3_smx:INFO:		Electrons
13:29:07:ST3_smx:INFO:	Total # of broken channels: 8
13:29:07:ST3_smx:INFO:	List of broken channels: [4, 5, 30, 33, 49, 56, 90, 118]
13:29:07:ST3_smx:INFO:	Total # of broken channels: 0
13:29:07:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:29:09:ST3_smx:INFO:	chip: 28-3 	 15.590880 C 	 1224.468235 mV
13:29:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:09:ST3_smx:INFO:		Electrons
13:29:14:ST3_smx:INFO:	Total # of broken channels: 6
13:29:14:ST3_smx:INFO:	List of broken channels: [63, 68, 78, 88, 90, 95]
13:29:14:ST3_smx:INFO:	Total # of broken channels: 0
13:29:14:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:29:16:ST3_smx:INFO:	chip: 26-5 	 34.556970 C 	 1165.571835 mV
13:29:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:16:ST3_smx:INFO:		Electrons
13:29:21:ST3_smx:INFO:	Total # of broken channels: 7
13:29:21:ST3_smx:INFO:	List of broken channels: [25, 50, 64, 72, 95, 107, 125]
13:29:21:ST3_smx:INFO:	Total # of broken channels: 0
13:29:21:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:29:22:ST3_smx:INFO:	chip: 24-7 	 28.225000 C 	 1189.190035 mV
13:29:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:29:22:ST3_smx:INFO:		Electrons
13:29:27:ST3_smx:INFO:	Total # of broken channels: 7
13:29:27:ST3_smx:INFO:	List of broken channels: [4, 6, 33, 41, 110, 113, 121]
13:29:27:ST3_smx:INFO:	Total # of broken channels: 0
13:29:27:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:29:28:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:29:28:febtest:INFO:	30-01 | XA-000-09-004-031-010-027-06 |  44.1 | 1153.7
13:29:28:febtest:INFO:	28-03 | XA-000-09-004-031-008-006-02 |  15.6 | 1242.0
13:29:28:febtest:INFO:	26-05 | XA-000-09-004-031-005-004-05 |  34.6 | 1195.1
13:29:28:febtest:INFO:	24-07 | XA-000-09-004-031-008-004-02 |  28.2 | 1212.7
{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 26_06_02-13_28_40
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2528| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9609', '1.848', '1.6250']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9851', '1.850', '1.3070']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9951', '1.850', '0.2645']
Comment