FEB_4352 19.02.26 08:48:28
Info
08:48:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:48:28:ST3_Shared:INFO: FEB-Microcable
08:48:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:48:28:febtest:INFO: Testing FEB with SN 4352
08:48:30:smx_tester:INFO: Scanning setup
08:48:30:elinks:INFO: Disabling clock on downlink 0
08:48:30:elinks:INFO: Disabling clock on downlink 1
08:48:30:elinks:INFO: Disabling clock on downlink 2
08:48:30:elinks:INFO: Disabling clock on downlink 3
08:48:30:elinks:INFO: Disabling clock on downlink 4
08:48:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:48:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:48:30:elinks:INFO: Disabling clock on downlink 0
08:48:30:elinks:INFO: Disabling clock on downlink 1
08:48:30:elinks:INFO: Disabling clock on downlink 2
08:48:30:elinks:INFO: Disabling clock on downlink 3
08:48:30:elinks:INFO: Disabling clock on downlink 4
08:48:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:48:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:48:30:elinks:INFO: Disabling clock on downlink 0
08:48:30:elinks:INFO: Disabling clock on downlink 1
08:48:30:elinks:INFO: Disabling clock on downlink 2
08:48:30:elinks:INFO: Disabling clock on downlink 3
08:48:30:elinks:INFO: Disabling clock on downlink 4
08:48:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
08:48:30:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
08:48:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:48:30:elinks:INFO: Disabling clock on downlink 0
08:48:30:elinks:INFO: Disabling clock on downlink 1
08:48:30:elinks:INFO: Disabling clock on downlink 2
08:48:30:elinks:INFO: Disabling clock on downlink 3
08:48:30:elinks:INFO: Disabling clock on downlink 4
08:48:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:48:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:48:30:elinks:INFO: Disabling clock on downlink 0
08:48:30:elinks:INFO: Disabling clock on downlink 1
08:48:30:elinks:INFO: Disabling clock on downlink 2
08:48:30:elinks:INFO: Disabling clock on downlink 3
08:48:30:elinks:INFO: Disabling clock on downlink 4
08:48:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:48:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:48:30:setup_element:INFO: Scanning clock phase
08:48:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:48:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:48:31:setup_element:INFO: Clock phase scan results for group 0, downlink 2
08:48:31:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXX____
Clock Delay: 32
08:48:31:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXX____
Clock Delay: 32
08:48:31:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:48:31:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:48:31:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXX____
Clock Delay: 33
08:48:31:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXX____
Clock Delay: 33
08:48:31:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:48:31:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
08:48:31:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
08:48:31:setup_element:INFO: Scanning data phases
08:48:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:48:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:48:36:setup_element:INFO: Data phase scan results for group 0, downlink 2
08:48:36:setup_element:INFO: Eye window for uplink 24: ___________XXXXX________________________
Data delay found: 33
08:48:36:setup_element:INFO: Eye window for uplink 25: _____________XXXXX______________________
Data delay found: 35
08:48:36:setup_element:INFO: Eye window for uplink 26: ______________XXXXXXX___________________
Data delay found: 37
08:48:36:setup_element:INFO: Eye window for uplink 27: _________________XXXXXXX________________
Data delay found: 0
08:48:36:setup_element:INFO: Eye window for uplink 28: ___________________XXXXXXX______________
Data delay found: 2
08:48:36:setup_element:INFO: Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
08:48:36:setup_element:INFO: Eye window for uplink 30: ____________________XXXXXXX_____________
Data delay found: 3
08:48:36:setup_element:INFO: Eye window for uplink 31: ___________________XXXXX________________
Data delay found: 1
08:48:36:setup_element:INFO: Setting the data phase to 33 for uplink 24
08:48:36:setup_element:INFO: Setting the data phase to 35 for uplink 25
08:48:36:setup_element:INFO: Setting the data phase to 37 for uplink 26
08:48:36:setup_element:INFO: Setting the data phase to 0 for uplink 27
08:48:36:setup_element:INFO: Setting the data phase to 2 for uplink 28
08:48:36:setup_element:INFO: Setting the data phase to 1 for uplink 29
08:48:36:setup_element:INFO: Setting the data phase to 3 for uplink 30
08:48:36:setup_element:INFO: Setting the data phase to 1 for uplink 31
08:48:36:setup_element:INFO: Beginning SMX ASICs map scan
08:48:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:48:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:48:36:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:48:36:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:48:36:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
08:48:36:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:48:36:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:48:36:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:48:36:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:48:37:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:48:37:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:48:37:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:48:37:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:48:38:setup_element:INFO: Performing Elink synchronization
08:48:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:48:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:48:39:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:48:39:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:48:39:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
08:48:39:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:48:39:febtest:INFO: Init all SMX (CSA): 30
08:48:47:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:48:47:febtest:INFO: 30-01 | XA-000-09-004-017-016-022-08 | 18.7 | 1195.1
08:48:47:febtest:INFO: 28-03 | XA-000-09-004-017-016-023-08 | 21.9 | 1189.2
08:48:48:febtest:INFO: 26-05 | XA-000-09-004-017-004-023-02 | 21.9 | 1189.2
08:48:48:febtest:INFO: 24-07 | XA-000-09-004-017-007-023-12 | 37.7 | 1135.9
08:48:49:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:48:51:ST3_smx:INFO: chip: 30-1 18.745682 C 1206.851500 mV
08:48:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:48:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:48:51:ST3_smx:INFO: Electrons
08:48:51:ST3_smx:INFO: # loops 0
08:48:52:ST3_smx:INFO: # loops 1
08:48:54:ST3_smx:INFO: # loops 2
08:48:56:ST3_smx:INFO: Total # of broken channels: 0
08:48:56:ST3_smx:INFO: List of broken channels: []
08:48:56:ST3_smx:INFO: Total # of broken channels: 0
08:48:56:ST3_smx:INFO: List of broken channels: []
08:48:58:ST3_smx:INFO: chip: 28-3 21.902970 C 1200.969315 mV
08:48:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:48:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:48:58:ST3_smx:INFO: Electrons
08:48:58:ST3_smx:INFO: # loops 0
08:49:00:ST3_smx:INFO: # loops 1
08:49:01:ST3_smx:INFO: # loops 2
08:49:03:ST3_smx:INFO: Total # of broken channels: 0
08:49:03:ST3_smx:INFO: List of broken channels: []
08:49:03:ST3_smx:INFO: Total # of broken channels: 0
08:49:03:ST3_smx:INFO: List of broken channels: []
08:49:05:ST3_smx:INFO: chip: 26-5 25.062742 C 1200.969315 mV
08:49:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:49:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:49:05:ST3_smx:INFO: Electrons
08:49:05:ST3_smx:INFO: # loops 0
08:49:06:ST3_smx:INFO: # loops 1
08:49:08:ST3_smx:INFO: # loops 2
08:49:10:ST3_smx:INFO: Total # of broken channels: 0
08:49:10:ST3_smx:INFO: List of broken channels: []
08:49:10:ST3_smx:INFO: Total # of broken channels: 0
08:49:10:ST3_smx:INFO: List of broken channels: []
08:49:12:ST3_smx:INFO: chip: 24-7 40.898880 C 1147.806000 mV
08:49:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:49:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:49:12:ST3_smx:INFO: Electrons
08:49:12:ST3_smx:INFO: # loops 0
08:49:13:ST3_smx:INFO: # loops 1
08:49:15:ST3_smx:INFO: # loops 2
08:49:17:ST3_smx:INFO: Total # of broken channels: 0
08:49:17:ST3_smx:INFO: List of broken channels: []
08:49:17:ST3_smx:INFO: Total # of broken channels: 0
08:49:17:ST3_smx:INFO: List of broken channels: []
08:49:17:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:49:17:febtest:INFO: 30-01 | XA-000-09-004-017-016-022-08 | 21.9 | 1230.3
08:49:18:febtest:INFO: 28-03 | XA-000-09-004-017-016-023-08 | 21.9 | 1224.5
08:49:18:febtest:INFO: 26-05 | XA-000-09-004-017-004-023-02 | 25.1 | 1224.5
08:49:18:febtest:INFO: 24-07 | XA-000-09-004-017-007-023-12 | 44.1 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 26_02_19-08_48_28
OPERATOR : Alois Alzheimer
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4352| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7663', '1.846', '1.1380']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9913', '1.850', '1.2970']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9727', '1.850', '0.2605']