DTL-STS tests database

Link to ladder: L8UL201022

Module [ Site: GSI] versions: M8UL2B2010222A2 | QR pdf

FEB_A: 1220 FEB_B: 2222

Thermally Tested in Hk.Hl.

Tested Uplinks in Hk.Hl.

-- Last status: 2026-03-05 13:05 [ Undef. status at Hk.Hl. ]

Desired grade: A

Link to Sensor: 26244 (Grade: A) -- size: 62x124 mm

Link to Heck Halle Module Test Page

History of statuses:

2026-03-05 13:05:00 { Uli Frankenfeld } [ Undef. status at Hk.Hl. ] GSI
2026-02-26 13:20:00 { Gnana Sindhu Subramanya } [ Tested in Hk.Hl. ]
2026-02-04 07:15:00 { Frederike Nickels } [ Undef. status at Hk.Hl. ] GSI
2026-02-02 16:30:00 { Anju Sharma } [ Tested in Hk.Hl. ] GSI
2025-02-10 09:31:00 { Lady CollazoSanchez } [ Tested in Hk.Hl. ] GSI
2025-01-30 11:33:00 { Lady CollazoSanchez } [ Test started in Hk.Hl. ] GSI
2025-01-20 14:41:00 { Oleksandr Suddia } [ Tested Ch Cl.Ro. ] GSI
2024-09-02 10:09:08 { } [ Bonded in Cl.Ro. ] GSI
2024-08-29 08:23:01 { } [ Tested Ch Cl.Ro. ]
2024-08-29 08:22:24 { } [ Tested Ch Cl.Ro. ]
2024-08-28 13:09:37 { } [ Bonded in Cl.Ro. ] GSI
2023-11-11 10:00:00 { Irakli Keshelashvili } [ Reserved ] GSI

Comments:

2026-03-18 11:29 { Christian Schmidt } ( chip cables ordered )
2026-03-05 13:04 { Uli Frankenfeld } ( multiple solutions: pending decision ASIC exchange scheduled )
2026-02-04 07:17 { Frederike Nickels } ( ODI failed N-side: asic1 UL1_N, asic2 UL1_P and UL0_N, P-side: asic0 UL1_N, asic1 UL1_P, asic 2 UL1_N )
2026-02-02 16:31 { Anju Sharma } ( Retested )

Workflow

WF_2025_01_31_12_41_20.pdf WF_2025_02_12_09_58_31.pdf WF_2025_10_20_07_35_43.pdf

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