DTL-STS tests database

Link to ladder: L8UR301122

Module [ Site: KIT] versions: M8UR3T4011224A2 | QR pdf

FEB_A: 3216 FEB_A: 3216 FEB_B: 4216 FEB_B: 4216

Thermally Tested in Hk.Hl.

Tested Uplinks in Hk.Hl.

-- Last status: 2026-03-26 09:21 [ Tested in Hk.Hl. ]

Desired grade: D

Link to Sensor: 12224 (Grade: D) -- size: 62x124 mm

Link to Heck Halle Module Test Page

History of statuses:

2026-03-26 09:21:00 { Gnana Sindhu Subramanya } [ Tested in Hk.Hl. ]
2026-03-25 15:56:00 { Gnana Sindhu Subramanya } [ Test started in Hk.Hl. ]
2026-03-16 17:05:00 { Johann Heuser } [ Shielding, Ret. and FIN mounted ] GSI
2026-03-12 14:20:00 { Carmen Simons } [ Tested Ch Cl.Ro. ] GSI
2026-03-12 10:39:00 { Oleksandr Suddia } [ Tested Ch Cl.Ro. ] GSI
2026-03-05 13:07:00 { Uli Frankenfeld } [ Undef. status at Hk.Hl. ] GSI
2026-02-26 13:53:00 { Gnana Sindhu Subramanya } [ Tested in Hk.Hl. ]
2026-02-25 14:11:00 { Kerstin Schuenemann } [ Undef. status at Hk.Hl. ] GSI
2026-02-12 14:55:00 { Gnana Sindhu Subramanya } [ Tested Uplinks ]
2025-09-11 19:00:00 { Lady CollazoSanchez } [ Tested in Hk.Hl. ] GSI
2025-09-09 13:58:00 { Lady CollazoSanchez } [ Test started in Hk.Hl. ] GSI
2025-08-04 12:07:00 { Henrik Herzenstiel } [ Tested Ch Cl.Ro. ] KIT
2023-11-11 10:00:00 { Irakli Keshelashvili } [ Reserved ] KIT

Comments:

2026-03-16 17:06 { Johann Heuser } ( Module fully repaired. Waiting for test in HL. )
2026-03-12 14:23 { Carmen Simons } ( chipcables N-side 2 and 7 exchanged due to ODI problems, ULX ASIC 1_UL0, on P-side ULX, ASIC 1_UL0 and ASIC 3_UL_0 )
2026-03-12 10:42 { Oleksandr Suddia } ( FEB A (ULX): -ASIC1 - UL1 to UL0 -ASIC3 - UL1 to UL0 FEB B (ULX, New chips): -ASIC1 - UL1 to UL0 -ASIC2 - New -ASIC7 - New )
2026-03-05 13:08 { Uli Frankenfeld } ( multiple solutions: ULX scheduled, Usage of UL0 only, ASIC exchange scheduled. )
2026-02-13 17:59 { Anju Sharma } ( ODI failed )

Workflow

WF_2025_09_04_13_35_48.pdf WF_2025_10_20_12_54_22.pdf

No documents uploaded yet.

⇧ Top