M7DL5B0001230B2 Early breakdown -> cleaned and rearranged microcables -> fixed 42 2025-03-18 15:14:54.296078
M7DL5B1001231B2 High current during IV -> dry out -> fixed 42 2025-03-18 15:15:57.78061
M8UL0T3010603B2 p-side ENC pattern 42 2025-03-18 15:17:28.550952
M8UL0T2010602B2 p-side ENC pattern 42 2025-03-18 15:17:34.909472
M8UL0B2010602A2 p-side ENC pattern 42 2025-03-18 15:19:08.1958
M8UL0B3010603A2 p-side ENC pattern 42 2025-03-18 15:19:13.277552
M8UL0B1010601A2 High noise spread in ASIC HW_6 p-side 42 2025-03-18 15:19:39.376591
M8UL2T1010221B2 NO breakdown 42 2025-03-18 15:21:47.930837
M8UL2T1010221B2 64 broken channels (48 on p-side & 16 on n-side) 42 2025-03-18 15:22:40.362902
M8UL2T2010222B2 Dry out and rearranging of the microcables solved the breakdown 42 2025-03-18 15:26:38.035637
M8UL2T0010220B2 Drying out and rearranging the microcables solved the breakdown. 42 2025-03-18 15:28:14.78916
M8UL2T0010220B2 41 broken channels (39 on n-side & 2 on p-side) 42 2025-03-18 15:33:05.737622
M4UL2T4110314B2 Grade and sensor number needs to be added 1 2024-06-05 13:12:17.069579 GSI
M4UL4T2010322B2 This module was built wrongly. 1 2024-06-24 15:04:36.893094 GSI
M5DL1T2101162A2 Sensor changed from 10243 to 17173 1 2024-07-05 09:48:56.978386 GSI
M4UL2T4110314B2 PASSED, since every second channel is working. see meeting 3.07.2024 2 2024-10-11 15:36:58.552892
M7UL1B0010390A2 failed IV 2 2024-10-16 11:18:43.37173
M4UL0T0010550B2 a cluster of 29 broken channels in ASIC HW 5 n-side (even channels) 42 2024-10-17 10:33:26.410256
M4UL2T4110314B2 51 broken channels 42 2024-10-17 10:36:37.306562
M4DL0T2001612A2 early breakdown -> dry out -> fixed 42 2024-10-24 14:39:54.332733
M4DL0T1001611A2 early breakdown -> dry out -> fixed 42 2024-10-24 14:40:12.451392
M4DL2T2001162A2 Breakdown at 330 V-> dry out -> fixed 42 2024-10-24 14:42:32.838999
M4DL2B0001160B2 Asymmetrical current 42 2024-10-24 14:43:02.76608
M4DL2B1001161B2 Asymmetrical current, 35 broken channels 42 2024-10-24 14:43:24.194742
M4DL2B2001162B2 44 broken channels in N-side (39 of them from ASIC HW 5) 42 2024-10-24 14:44:35.931698
M4DL4T2001172A2 Short circuit between the ground plane and ground of the carrier on the n-side (red FEB) -> fixed 42 2024-10-24 14:48:08.353267
M5UL1B0010160A2 Breakdown at 370V -> dry out -> fixed 42 2024-10-24 14:54:51.248237
M5UL1B1010161A2 Asymmetrical Current 42 2024-10-24 14:55:33.209507
M5UL1B2010162A2 Asymmetrical Current 42 2024-10-24 14:55:37.053194
M5UL1B3010163A2 Asymmetrical Current 42 2024-10-24 14:55:39.403675
M5UL5T2010182B2 ASIC HW 0 (n-side) no good calibration (the applied pulse generation doesn't work) 42 2024-10-24 14:57:32.542631
M5DL1T2101162A2 Breakdown at 420V -> fixed 42 2024-10-24 15:01:06.553239
M6UL0T1010571B2 Asymmetrical current 42 2024-10-24 15:06:10.521308
M6UL0T0010570B2 Breakdown at 430 V -> dry-out -> fixed 42 2024-10-24 15:06:40.189402
M6UL0B0010570A2 Asymmetrical current 42 2024-10-24 15:06:58.965182
M6UL0B1010571A2 High noise level on ASIC HW 0 n-side -> odd channels are fine, even channels with high noise 42 2024-10-24 15:08:07.86608
M6UL0B2010572A2 High noise ASIC HW 3 (p-side) -> odd channels are fine, even channels with high noise 42 2024-10-24 15:09:22.232832
M6UL2T3010353B2 Asymmetrical current 42 2024-10-24 15:09:56.13026
M6UL2T0010350B2 Asymmetrical current 42 2024-10-24 15:10:17.659255
M6UL2B0010350A2 Asymmetrical current 42 2024-10-24 15:10:39.398978
M6UL2B1010351A2 Breakdown at 400 V -> dry out -> fixed 42 2024-10-24 15:10:54.973477
M6UL4T0010360B2 Early breakdown -> dry out -> fixed 42 2024-10-24 15:12:36.244635
M6UL4B1010361A2 Asymmetrical current 42 2024-10-24 15:12:54.163635
M6UL4B2010362A2 Asymmetrical current 42 2024-10-24 15:12:57.577121
M6DL2T1001201A2 Asymmetrical current 42 2024-10-24 15:16:49.146456
M6DL2T0001200A2 Asymmetrical current 42 2024-10-24 15:16:51.707882
M6DL2B0001200B2 Breakdown at 350V -> dry-out -> fixed 42 2024-10-24 15:17:13.170966
M6DL4T1001201A2 Asymmetrical current 42 2024-10-24 15:18:23.873651
M6DL4T0001200A2 Asymmetrical current 42 2024-10-24 15:18:26.153647
M6DL4B0001200B2 Asymmetrical current 42 2024-10-24 15:18:28.565577
M6DL4B1001201B2 Asymmetrical current 42 2024-10-24 15:18:30.857535
M6DL4B2001202B2 Asymmetrical current 42 2024-10-24 15:18:33.565946
M6DL4B3001203B2 Asymmetrical current 42 2024-10-24 15:18:35.284114
M6DL4B4001204B2 Asymmetrical current 42 2024-10-24 15:18:37.366514
M8UL4B0010220A2 62 broken channels (45 on n-side & 17 on p-side) 42 2025-03-18 15:45:05.036777
M8UL6T2010242B2 p-side ENC pattern 42 2025-03-18 15:53:31.494923
M8UL6B2010242A2 28 broken channels 42 2025-03-18 15:58:57.311099
M3DR4T2000132B2 ASIC HW_7 p-side has higher noise level on even channels 42 2025-03-18 16:06:12.880084
M3DR4B2000132A2 p-side ENC pattern 42 2025-03-18 16:08:42.120909
M3DR4B3000133A2 p-side ENC pattern 42 2025-03-18 16:09:06.302485
M3DR6T0000150B2 p-side ENC pattern 42 2025-03-18 16:11:35.271909
M3DR6B0000150A2 Slow breakdown ~ 50V 42 2025-03-18 16:12:13.990308
M4UR1T1011311A2 p-side ENC pattern 42 2025-03-18 16:14:15.623486
M5UR0T3011563A2 p-side ENC pattern 42 2025-03-18 16:18:40.186325
M5UR6B0011190B2 High current during IV -> dry out -> fixed 42 2025-03-18 16:26:30.833939
M3DR2T4000124B2 Slow breakdown ~ 175 V -> dry out 42 2025-03-20 11:47:58.830448
M3DR2B3000123A2 p-side ENC pattern 42 2025-03-20 11:51:37.901881
M3DR2B4000124A2 p-side ENC pattern 42 2025-03-20 11:51:46.903686
M4DR1T0000160B2 Breakdown ~ 330V -> fixed 42 2025-03-20 13:55:38.142553
M3DR6B0000150A2 bad IV 10 uA, 125 V 76 2025-03-25 14:14:32.457188
M7UL3B2010392A2 does not hold 350 V, just 225 76 2025-03-25 14:27:55.842318
M7DL3B3001223B2 just reaches 250V at almost 10 uA --> fair IV --> use it 76 2025-03-25 14:39:57.065275
M5DL1B0001160B2 Bad IV during ladder test: 10 uA@85 V 7 2025-03-25 14:49:16.772825
M5DL1T0001160A2 N uplink_1 driver defect R to GND (20Ω*2) defect 7 2025-03-25 14:56:08.06446
M5DL1T1001161A2 P uplink_1 driver defect 7 2025-03-25 14:58:05.422094
M3DR2T3000123B2 p-side ENC pattern 42 2025-03-25 23:37:52.495257
M4UR5T1011331A2 p-side ENC pattern 42 2025-03-25 23:42:07.311771
M4UR5B1011331B2 p-side ENC pattern 42 2025-03-25 23:43:26.836925
M4DR1B1000161A2 29 broken channels 42 2025-03-25 23:46:16.606692
M4DR1T0000160B2 Breakdown ~ 330 V -> fixed after release of the microcables clamps 42 2025-03-25 23:48:28.1993
M4DR1T1000161B2 56 broken channels 42 2025-03-25 23:49:23.201924
M4DR1T1000161B2 56 broken channels 42 2025-03-25 23:49:23.896008
M8UL2T1010221B2 fix DB 7 2025-10-07 09:18:11.023803 GSI
M6DL6T0001270A2 24 broken channels, from them a cluster of 13 broken channels close to the edge of ASIC HW 7 p-side 42 2024-10-24 15:19:54.195341
M6DL0T3001583A2 32 broken channels (28 of them are from ASIC HW 1 n-side) 42 2024-10-24 15:32:42.571026
M6DL0T3001583A2 32 broken channels (28 of them are from ASIC HW 1 n-side) 42 2024-10-24 15:33:22.561308
M6DL0B1001581B2 59 broken channels(44 of them in ASIC HW 7 p-side) 42 2024-10-24 15:35:16.445901
M7UL1T1010391B2 Early breakdown -> dry out -> fixed 42 2024-10-24 15:38:17.674812
M7UL1T0010390B2 Early breakdown -> dry out -> Breakdown at 340 V -> fixed 42 2024-10-24 15:39:21.198413
M7UL1B1010391A2 Asymmetrical current -> Try to measure ENC but very high current appears -> IV measurement again, no asymmetric current, but some spike in p-side -> Measure ENC again & result is OK 42 2024-10-24 15:41:33.715876
M7UL5T2010402B2 Short circuit in N-side 42 2024-10-24 15:43:17.599906
M7UL5B1010401A2 Early breakdown -> dry out -> fixed 42 2024-10-24 15:44:05.09027
M7UL7B0010410A2 Spike around 160V during IV, behavior as expected -> dry out because of 0.4mA at 40V during operation -> fixed 42 2024-10-24 15:45:31.730546
M7DL7T0001260A2 Early breakdown -> dry out -> fixed 42 2024-10-24 15:47:43.591444
M7DL7B1001261B2 Slow breakdown ~ 130V -> dry-out -> Not improvement, but since the module has a sensor grade D we decided to use it in these conditions 42 2024-10-24 15:49:23.855377
M8UL0T0010600B2 Breakdown ~ 420 V -> dry out -> fixed & 33 broken channels (10 on n-side and 23 on p-side) 42 2024-11-25 17:38:29.15606
M5UR0T2011562A2 module was build at GSI. 5 2024-11-28 10:57:47.756473
M6UL4T3110363B2 36 broken channels (8 on n-side and 28 on p-side, 22 of them consecutive) 42 2024-12-09 23:01:40.252157
M7UL1T0010390B2 Early breakdown ~ 5V -> dry out -> fixed 42 2024-12-17 21:55:46.155293
M7DL3T3001223A2 Slow breakdown ~ 120 V 42 2024-12-17 22:00:33.934351
M7DL3B3001223B2 Slow breakdown ~ 150 V 42 2024-12-17 22:01:32.176964
M7UL1B0110390A2 35 broken channels on n-side and 34 broken channels on p-side (69 in total) 42 2025-01-14 10:48:01.683397
M3DR0B1000541A2 Slow breakdown ~ 350V ( ~ 3uA at 500 V) 42 2025-01-27 08:46:02.730437
M8UL2T2010222B2 Sharp breakdown at 375V (Optical grade A) 77 2025-02-11 11:27:43.657608
M8UL2T1010221B2 Sharp breakdown at 375V (Optical grade A) 77 2025-02-11 11:28:01.26966
M8UL2T2010222B2 Sharp breakdown at 370V 77 2025-02-11 11:28:38.649548
M8UL2T2010222B2 Sharp breakdown at 370V 77 2025-02-11 11:29:33.573354
M8UL2T2010222B2 Sharp breakdown at 370V 77 2025-02-11 11:30:22.158148
M8UL2T2010222B2 presented by Anju on 12.02.2025 --> breakdown at > 350 V --> maybe class B (from A) 76 2025-02-13 13:37:13.883163
M4UR1T2011312A2 presented by Anju 12.02.2025 current breakdown at 350V, required grade: A 76 2025-02-13 13:41:23.567501
M8UL2T0010220B2 reported by Anju on 12.02.2025 passed with errors: M8UL2T0010220B2 Reason: 41 broken channels (39 on n-side and 2 on p-side) but current breakthrough at 370 V 76 2025-02-13 13:51:38.473179
M8UL2T0010220B2 presented by Anju on 22.01.2025 current increase from 100 V, does not reach 200 V 76 2025-02-13 14:17:15.728269
M7DL3B3001223B2 current rises from 150 V to just below 10 uA at 250V required class C, seems just to reach C 76 2025-02-13 14:22:28.879513
M8UL2T2010222B2 B but required A 76 2025-02-13 14:25:38.899943
M7DL3T3001223A2 required C, but does not reach 200 V 76 2025-02-14 13:12:48.626362
M5UR0B3011563B2 IV grade C still acceptable. Thus to be used. 76 2025-02-24 10:47:09.260675
M4DR3B1000171A2 New sensor 15193 assigned due to scratch on old sensor with id 08063 1 2025-02-27 15:41:20.998386
M4DL0T3001613A2 Noisy channels in ASIC HW 7 and 6 p-side 42 2025-03-18 13:53:47.746722
M4DL0B3101613B2 p-side ENC pattern -> Fixed 42 2025-03-18 14:00:15.333284
M4DL4T3001173A2 p-side ENC pattern 42 2025-03-18 14:18:43.146653
M4DL4B3001173B2 p-side ENC pattern 42 2025-03-18 14:27:35.273182
M4DL6B1001191B2 p-side ENC pattern 42 2025-03-18 14:28:25.667557
M5UL5T0010180B2 p-side ENC pattern 42 2025-03-18 14:30:57.944421
M5DL3B3001173B2 p-side ENC pattern 42 2025-03-18 14:32:08.48504
M6UL4B3010363A2 ENC pattern 42 2025-03-18 14:36:41.675812
M6DL0T4001584A2 p-side ENC pattern 42 2025-03-18 14:37:40.590206
M6DL0T2001582A2 p-side ENC pattern 42 2025-03-18 14:38:30.38897
M6DL0B2001582B2 p-side ENC pattern 42 2025-03-18 14:39:11.105358
M6DL0B4001584B2 p-side ENC pattern 42 2025-03-18 14:39:37.417268
M6DL2B2001202B2 p-side ENC pattern 42 2025-03-18 14:41:08.964232
M6DL2B4001204B2 p-side ENC pattern 42 2025-03-18 14:41:20.427988
M6DL4T0001200A2 NO asymmetrical current 42 2025-03-18 14:43:58.517215
M6DL4B0001200B2 NO asymmetrical current 42 2025-03-18 14:44:03.123002
M6DL4B1001201B2 NO asymmetrical current 42 2025-03-18 14:44:06.177874
M6DL4B2001202B2 NO asymmetrical current 42 2025-03-18 14:44:09.033857
M6DL4B3001203B2 NO asymmetrical current 42 2025-03-18 14:44:11.093904
M6DL4B4001204B2 NO asymmetrical current 42 2025-03-18 14:44:13.389361
M6DL4B4001204B2 p-side ENC pattern 42 2025-03-18 14:44:33.690064
M7UL3T4010394B2 Two ASICs in n-side HW_4 and HW_6 with the same E-fuse ID (XA-000-08-003-000-006-051-08) 42 2025-03-18 14:48:11.726934
M7UL3T2010392B2 High current during IV and calibration ~ 5uA 42 2025-03-18 14:49:20.370871
M7UL3T1010391B2 Breakdown ~ 450 V 42 2025-03-18 14:50:09.384608
M7UL3T0010390B2 All ASICs except HW_1 n-side with the same E-fuse ID (XA-000-08-003-000-006-051-08) 42 2025-03-18 14:52:00.11015
M7UL3B0010390A2 All ASICs p-side with the same E-fuse ID (XA-000-08-003-000-006-051-08) 42 2025-03-18 14:52:45.690162
M7UL3B1010391A2 Slow breakdown ~ 475 V 42 2025-03-18 14:53:37.619635
M7UL3B2010392A2 Slow breakdown ~ 125 V 42 2025-03-18 14:54:27.242753
M7DL1T4001224A2 p-side ENC pattern 42 2025-03-18 15:00:43.662361
M7DL1B4001224B2 p-side ENC pattern 42 2025-03-18 15:01:22.687196
M7DL3T1001221A2 p-side ENC pattern 42 2025-03-18 15:09:00.524309
M7DL3T0001220A2 Multiple ASICs with the same E-fuse ID 42 2025-03-18 15:09:52.32503
M7DL3B0001220B2 37 broken channels (36 on n-side & 1 on p-side) 42 2025-03-18 15:11:21.463068
M7DL3B4001224B2 ENC pattern 42 2025-03-18 15:12:25.096061
M7DL5T4001234A2 High leakage current -> fixed 42 2025-03-18 15:13:24.340023
M8UL2T3010223B2 ENC pattern 42 2025-03-18 15:20:29.551162
M5UR4B0011170B2 Repaired in CL 7 2025-04-02 09:09:33.054151
M5DL1T2101162A2 Removed from Ladder; To be used 7 2025-04-04 09:08:25.147208
M5DL1T3001163A2 Removed from Ladder; To be used 7 2025-04-04 09:10:18.941953
M5DL1T4001164A2 Removed from Ladder; To be used 7 2025-04-04 09:10:52.695638
M4DR1B3000163A2 39 broken channels 42 2025-04-04 15:04:17.665993
M4DR1B4000164A2 p-side ENC pattern 42 2025-04-04 15:05:01.166133
M4DR3T3000173B2 Early breakdown -> fixed by removing microcable clamps p-side ENC pattern 42 2025-04-04 15:07:59.071744
M4DR3T0000170B2 p-side ENC pattern 42 2025-04-04 15:10:05.106759
M5DL1B0101160B2 Module created 1 2025-04-16 16:07:44.817034
M5DL1T0101160A2 Module created 1 2025-04-16 16:08:57.568855
M5DL1T1101161A2 Module created 1 2025-04-16 16:10:27.543354
M5DR2T1100161B2 Module created 76 2025-04-25 11:15:20.178697
M5DR2T1000161B2 old sensor ID restored 76 2025-04-25 11:10:00 GSI
M5DR2T1000161B2 By J.H.s request, the sensor has been updated to M5DR2T1000161B2 -> 03422 1 2025-04-08 11:03:52.992359 GSI
M7UL3T3010393B2 pending (recorded by Patryck Semeniuk) 76 2025-04-28 14:54:05.263301
M6UL6B0010380A2 Fix Status in DB 7 2025-04-28 15:10:47.862023
M4UR1B1011311B2 Very slow breakdown is starting at ~475V; At 500V leakage current value = 1,5 uA 42 2025-04-29 10:14:15.138206
M4UR1B1011311B2 Very slow breakdown is starting at ~475V; At 500V leakage current value = 1,5 uA 42 2025-04-29 10:31:40.975809
M4UR3T4011314A2 p-side ENC pattern 42 2025-04-29 10:35:25.748471
M5UR2T4011164A2 Ohmic behaviour, leakage current value = 1,4 uA at 250V 42 2025-04-29 10:41:42.779861
M5UR2B0011160B2 Little asymmetric current for p- and n-side 42 2025-04-29 10:43:36.678508
M5UR2B3011163B2 Ohmic behavior, leakage current value = 6.5 μA at 350 V. Higher ENC level on p-side ASIC HW address 0 42 2025-04-29 10:45:14.351221
M3DR4T0000130B2 P-side shielding is broken, needs to be re-mounted 42 2025-05-07 11:44:14.560355
M4DR5B2000182A2 Broken sensor, clean cut 42 2025-05-14 09:41:26.865918
M4DL4T2001172A2 10 uA @ 4V after Ladder assembly. Removed from ladder. 7 2025-05-20 21:46:43.158952
M4DL4B2001172B2 10 uA @ 4V after Ladder assembly. Removed from ladder. 7 2025-05-20 21:49:58.459183
M5DR0B3000563A2 36 broken channels on the n-side 42 2025-05-20 23:53:32.049454
M3DL3T4001124A2 Soft breakdown 7 2025-05-23 09:59:09.780532
M3DL5B0001140B2 Soft breakdown 7 2025-05-23 09:59:51.153266
M3DL5B0001140B2 Hard breakdown at various voltages 7 2025-05-23 10:01:06.878925
M4DL0B3001613B2 Soft breakdown 7 2025-05-23 10:01:35.85718
M4UL2T3010313B2 Hard breakdown@450 V. New grade B 7 2025-05-23 10:02:52.6934
M4UL2T4010314B2 Soft breakdown 7 2025-05-23 10:03:25.775279
M5UL3T0010170B2 High ohmic (parallel) current 7 2025-05-23 10:09:09.581756
M6UL0B3010573A2 Breakdown @15V 7 2025-05-23 10:09:54.119001
M6UL0B3010573A2 After storage in cleanroom: Breakdown @ 55V 7 2025-05-23 10:11:25.296398
M6UL0B3010573A2 After measurement up to 15 uA and 14h @ 200V: Grade C (7.5 uA@250V) 7 2025-05-23 10:12:51.129782
M6UL4T3010363B2 High ohmic (parallel) current 7 2025-05-23 10:13:48.095241
M7UL1B0010390A2 Hard breakdown@325 V: New grade C 7 2025-05-23 10:15:06.564349
M7DL3T3001223A2 Soft breakdown 7 2025-05-23 10:20:56.212624
M5DL1T0001160A2 Failed during ladder test: Short between T0 and T1. 7 2025-05-23 10:22:47.492593
M5DL1T1001161A2 Failed during ladder test: Short between T0 and T1. 7 2025-05-23 10:23:27.595331
M4DR5B2000182A2 Fixed status in db; Sensor broken before start of module test. 7 2025-05-23 10:31:19.869938
M3DL5B0001140B2 ERRATUM: Soft breakdown 7 2025-05-23 10:34:20.832157
M5DL1T2001162A2 High ohmic (parallel) current 7 2025-05-23 10:36:14.069842
M4DL0B1001611B2 Hard breakdown at various voltages 7 2025-05-23 10:37:25.483918
M4UL6T0010340B2 This module was built wrongly. 7 2025-05-23 10:38:58.713639
M5DR2T1000161B2 This module was built wrongly. 7 2025-05-23 10:39:46.912314
M6UL6B0010380A2 This module was built wrongly. 7 2025-05-23 10:41:05.730671
M5DR4T3000173B2 41 broken channels (32 on the p-side and 9 on the n-side) 42 2025-06-11 11:09:57.902958 GSI
M5UR2T3011163A2 Not smooth IV 42 2025-06-17 15:20:10.912634 GSI
M5DR0T1000561B2 ASIC 6 p-side, issues with calibration -> every four channels, the internal pulse generator is not working 42 2025-06-17 15:33:38.76449 GSI
M4UR1T2011312A2 This module has been exchanged with M4UR3T2011312A2 1 2025-06-25 13:55:16.445733 GSI
M4UR3T2011312A2 This module has been exchanged with M4UR1T2011312A2 1 2025-06-25 13:55:42.764994 GSI
M6DL4B0001200B2 First 22mm sensor on ladder 7 2025-06-25 14:48:42.031667 GSI
M4UR3T2011312A2 holds 340V -- accepted as grade B 76 2025-06-26 13:47:37.302334 GSI
M4UR1T2011312A2 passed - grade A 76 2025-06-26 13:49:35.432048 GSI
M4DL4T2101172A2 Module created 76 2025-06-26 13:55:26.05136 GSI
M4DR5B2100182A2 Module created 76 2025-06-26 13:57:47.790942 GSI
M3DR6B0100150A2 Module created 76 2025-06-26 15:12:01.889067 GSI
M7UL3B2110392A2 Module created 76 2025-06-26 15:13:32.389024 GSI
M5UR2B4011164B2 Early breakdown 42 2025-07-01 11:15:08.983669 GSI
M6UR1T4011354A2 early breakdown -> dry out 42 2025-07-01 11:42:17.441815 GSI
M6UR1T3011353A2 early breakdown -> dry out 42 2025-07-01 11:42:27.553053 GSI
M6UR1T2011352A2 Breakdown ~ 440V -> dry out -> fixed 42 2025-07-01 11:45:31.831552 GSI
M6UR1T0011350A2 Breakdown ~ 480 V -> dry out 42 2025-07-01 11:52:25.984307 GSI
M6UR1B3011353B2 Early breakdown 42 2025-07-01 11:55:26.829577 GSI
M6UR1B2011352B2 asymmetric current 42 2025-07-01 11:57:17.231136 GSI
M6UR3T2011362A2 ohmic behavior 42 2025-07-01 13:37:11.090308 GSI
M6UR3B3011363B2 ohmic behavior 42 2025-07-01 13:38:25.927543 GSI
M5DR6T0000190B2 Uplinks on n-side are missing, reported on 18 June 2025. Most likely an LV over-voltage to FEB happened during testing. 76 2025-07-01 14:02:04.160235 GSI
M4DR5T0000180B2 Uplinks are missing, reported on 18 June 2025. Most likely an LV over-voltage to FEB happened during testing. 76 2025-07-01 14:03:18.485443 GSI
M5DR0T2000562B2 Uplinks are missing, reported on 18 June 2025. Most likely an LV over-voltage to FEB happened during testing. 76 2025-07-01 14:04:02.780394 GSI
M5DR6T0000190B2 Actually: Human mistake in handling during final acceptance test 76 2025-07-02 10:28:32.281941 GSI
M6UR3B0011360B2 asymmetric current 42 2025-06-01 13:39:04 GSI
M4DR5T0000180B2 Actually: Human mistake in handling during final acceptance test 76 2025-07-02 10:29:37.492435 GSI
M5DR0T2000562B2 Actually: Human mistake in handling during final acceptance test 76 2025-07-02 10:30:12.802124 GSI
M7UL3T3010393B2 sensor holds almost 250V, at 10 uA, thus is considered as good for the required grade C. 76 2025-07-02 10:35:34.978885 GSI
M6UR1T0011350A2 Slow breakdown ~ 480V -> @ 500V ~ 0.6 uA 42 2025-07-03 13:51:57.001178 GSI
M6UR3B3011363B2 Ohmic parallel currents 42 2025-07-03 14:01:39.891034 GSI
M5DR0T2100562B2 Module created 76 2025-07-04 10:18:12.5764 GSI
M5DR6T0100190B2 Module created 76 2025-07-04 10:20:36.297486 GSI
M4DR5T0100180B2 Module created 76 2025-07-04 10:22:14.499439 GSI
M6UR3T3011363A2 Early breakdown/ High leakage current (18 uA at the Start of Tests) -> 12 uA at the End of the Test 42 2025-07-14 10:27:59.169819 GSI
M6UR5T2011372A2 High current ~ 27uA at 150 V 42 2025-07-14 10:52:30.3334 GSI
M7UR2B4011394B2 High leakage current on measuring day (60 uA at the start of the test), 31 uA at the end of the test 42 2025-07-14 11:25:47.641043 GSI
M7UR6T0011260A2 Current fluctuations between 60 and 80 V 42 2025-07-14 11:34:52.982465 GSI
M5DR2B3000163A2 ASIC HW 7 on n- and p-side. Indicious of the pulse generator not working in the p-side 42 2025-07-14 11:38:54.4848 GSI
M8UR7B1011261B2 High current ~ 45uA at 150V 42 2025-07-14 11:47:39.044604 GSI
M8UR7T0011260A2 High current ~ 40 uA at 150 V 42 2025-07-14 11:51:00.316008 GSI
M6UR1B3011353B2 High current ~ 15 uA @ 150 V. Rising current @ 340 V. It reached the 350 V with I = 42 uA 42 2025-07-15 18:16:59.985248 GSI
M6UR1B4011354B2 High current ~ 32 uA @ 150V. Current fluctuations from 210 - 250 V. 42 2025-07-15 18:23:37.658421 GSI
M6UR3T2011362A2 High current with large fluctuations. Stable curve from 170 - 315 V. i = 8uA @ 150V 42 2025-07-15 18:29:32.649322 GSI
M6UR5B1011371B2 High current ~ 50 uA @ 150 V 42 2025-07-15 18:32:44.525018 GSI
M6DR5B2000252A2 Every four channels of ASIC HW_1 p-side are very noisy 42 2025-07-15 18:40:47.010494 GSI
M7UR2B2011392B2 Current fluctuations with spike at 60 V -> Bias run overnight -> No spike, but a bit higher current from 0 - 60 V 35 broken channels (34 in n-side and one on p-side) 42 2025-07-15 18:50:42.923557 GSI
M5UR2B4011164B2 ??? pending? 76 2025-07-18 16:21:13.276234 GSI
M5UR2B4111164B2 Module created 76 2025-07-18 16:25:37.803746 GSI
M7UR6B0011260B2 Sensor corner damaged during test/handling 76 2025-07-18 16:35:38.112862 GSI
M7UR6B0111260B2 Module created 76 2025-07-18 16:38:33.567196 GSI
M6DL0B4101584B2 Module created 76 2025-07-18 16:44:23.696599 GSI
M5DL3B2001172B2 ODI all ok 4 2026-03-25 13:43:29.315397 GSI
M6DR3T0000200B2 Breakdown at 470V. It reaches 500V with i = 12uA 42 2025-07-22 11:46:23.007028 GSI
M6DR3B2000202A2 Slow Breakdown ~ 340V 42 2025-08-01 11:40:43.593515 GSI
M6DR3B4000204A2 slow bd at 125V, current at 150V (i=3microA) and current at EOF(i=10microA) 42 2025-08-01 11:46:30.803417 GSI
M5UR0B3011563B2 74 broken channels (5 on p-side and 67 on n-side). 62 of the n-side broken channels are located in the ASIC HW 6 42 2025-08-12 11:05:06.771619 GSI
M7UR0T2011592A2 Asymmetric current 42 2025-08-12 11:10:47.5664 GSI
M7UR0B0011590B2 Asymmetric current. Slow breakdown at ~ 430 V, I = 5.5 uA at EOL voltage 42 2025-08-12 11:22:25.014143 GSI
M7UR4T2011392A2 Asymmetric current 42 2025-08-12 11:29:53.994541 GSI
M7UR4T1011391A2 Asymmetric current 42 2025-08-12 11:31:21.698674 GSI
M7UR4T0011390A2 Asymmetric current 42 2025-08-12 11:34:24.519643 GSI
M7UR4B3111393B2 Module created 1 2025-08-13 11:06:09.558636 GSI
M7UR4B3011393B2 The sensor is broken. 1 2025-08-13 11:07:12.374151 GSI
M6UL4T0010360B2 IV after LA: first breakdown, then separate and arrange cables: perfect IV 75 2025-08-19 09:00:29.171417 GSI
M0DL2T3001093A2 ENC pattern all over p-side 42 2025-08-19 10:49:24.642084 GSI
M6UR1T2011352A2 Breakdown at 440V -> Dryout -->Resolved. Uplinks 4 and 5 (ASIC HW_2) are missing on N-SIDE. 42 2025-08-19 11:20:19.187756 GSI
M7UR2T2011392A2 Issue in ASIC HW_3 on n-side (bits are stuck on 243) 42 2025-08-19 11:29:07.395651 GSI
M7UR4B4011394B2 A spike at 10V, asymmetric current after 20V. 42 2025-08-19 11:36:17.319743 GSI
M6UL4T1010361B2 The module has a special connection from the p-side FEB to ground. Resistance between FEB and ground: P-Side: 7.1Ω, N-side: 0.3Ω. 75 2025-08-21 09:36:57.364838 GSI
M6UL4T1010361B2 on the sensor a (very) small part of the corner is not there 75 2025-08-27 10:35:41.957633 GSI
M6UL4B2010362A2 high currentasfter ladder assembly, biased overnight, then 250V at 8 micro A 75 2025-08-27 10:38:56.516592 GSI
M6UR1T4011354A2 Tested at LAD Assembly 22.08.2025. J. Heuser desided module ok. 75 2025-08-28 10:22:02.454801 GSI
M6UR1T3011353A2 Tested at LAD Assembly 28.08.2025. J.Heuser desided: module failed. 75 2025-08-28 10:27:24.695552 GSI
M6UR1T3111353A2 Module created 1 2025-08-28 14:44:28.114152 GSI
M0DR1T1100091B5 Module created 1 2025-08-28 15:47:56.653555 GSI
M0DR1T1000091B5 Modul assembled wrongly (P and N Side were swapped) 76 2025-08-28 15:52:30.36509 GSI
M6UL2T0010350B2 scratches on the P-Side before LA, IV ok 75 2025-09-02 11:28:16.620515 GSI
M6UL2T0010350B2 short circuit after ladder assembly 75 2025-09-05 13:03:54.618167 GSI
M4DL4B2101172B2 resistance to ground 5k Ohm, resistance FEB A to FEBB 0.3 Ohm, resistance Fin to Base 0.3 Ohm, 75 2025-09-09 10:03:47.100841 GSI
M6UL2T0110350B2 Module created 76 2025-09-17 13:51:52.03633 GSI
M8UR1T2011222A2 Spike at 250 to 275V and Asymmetric current. Resolved after dry out, but showing bd at 340V (grade A) 42 2025-09-24 13:48:22.697662 GSI
M8UR1T1011221A2 75 broken channels (53 on n-side and 22 on p-side) 42 2025-09-24 13:51:43.088458 GSI
M8UR3T2011222A2 75 broken channels (68 on p-side and 7 on n-side) 42 2025-09-24 14:05:41.230327 GSI
M8UR5T4011234A2 Asymmetric current 42 2025-09-24 14:12:35.34526 GSI
M8UR5T0011230A2 Asymmetric current 42 2025-09-24 14:13:11.921657 GSI
M8UR5B0011230B2 Asymmetric current 42 2025-09-24 14:16:45.322074 GSI
M8UR5B1011231B2 Asymmetric current 42 2025-09-24 14:17:23.750791 GSI
M8UR5B2011232B2 Asymmetric current 42 2025-09-24 14:17:58.380346 GSI
M8UR5B3011233B2 Asymmetric current 42 2025-09-24 14:18:36.314136 GSI
M8UR5B4011234B2 Asymmetric current 42 2025-09-24 14:19:00.207207 GSI
M7DL1T0001220A2 Resistance to ground 3 Ohm 75 2025-09-26 10:09:49.082231 GSI
M7DL1T0001220A2 Resistance to ground 3 Ohm 75 2025-09-26 10:10:41.705777 GSI
M7DL1T0001220A2 Resistance to ground 3 Ohm 75 2025-09-26 10:12:16.316335 GSI
M7DL1T0001220A2 Resistance to ground 3 Ohm 75 2025-09-26 10:12:45.654025 GSI
M7DL1T0001220A2 Resistance to ground 3Ohm 75 2025-09-26 10:13:12.22806 GSI
M7DR2B1000221A2 37 broken channels (33 on n-side and 4 on p-side) 42 2025-09-29 14:31:18.1787 GSI
M7DR2T2000222B2 36 broken channels (28 on n-side and 8 on p-side) 42 2025-09-29 14:35:06.051894 GSI
M7DR6T1000241B2 35 broken channels (27 on n-side and 8 on pside) 42 2025-09-29 14:42:11.464835 GSI
M7DL1T1001221A2 There is glue on the contacts for the power cables 75 2025-10-01 08:46:39.408489 GSI
M7DL1B3001223B2 Sensor broken before LA 75 2025-10-01 12:55:13.553048 GSI
M8UL2T3010223B2 fix DB 7 2025-10-07 09:09:45.352668 GSI
M0DR1T2000092B2 fix DB 7 2025-10-07 09:17:08.931764 GSI
M8UL4B4010224A2 fix DB 7 2025-10-07 09:19:05.080631 GSI
M7DL3B3001223B2 Slow breakdown at 150V 77 2025-10-07 11:06:34.748051 GSI
M5UR0B3011563B2 Ohmic behaviour 77 2025-10-07 11:14:19.115697 GSI
M4UL2T3010313B2 14 uA @ 3 V 7 2025-10-09 09:33:51.097017 GSI
M4UL2T3010313B2 Module at an Exhibition 7 2025-10-09 09:34:39.687312 GSI
M7DR4T1000221B2 Sensor broken in pieces 7 2025-10-09 09:38:23.167362 GSI
M7DL1B3001223B2 Sensor broken in pieces 7 2025-10-09 09:54:05.896805 GSI
M3UL5B0010140A2 Wrong cables bonded on first sensor side 7 2025-10-09 09:55:11.688711 GSI
M3UL5B1010141A2 Wrong cables bonded on first sensor side 7 2025-10-09 09:55:58.66528 GSI
M4UR1T2011312A2 M4UR1T2011312A2 nach Modultausch (alt: M4UR3T201131A) 1 2025-10-09 11:06:05.597488 GSI
M4UR3T2011312A2 M4UR1T2011312A2 nach Modultausch (alt: M4UR1T2011312A2) 1 2025-10-09 11:06:52.125607 GSI
M8UR1T1011221A2 75 broken channels 77 2025-10-15 10:23:30.297804 GSI
M8UR3T2011222A2 75 broken channels----> Pending 77 2025-10-15 10:33:42.918421 GSI
M8UR1T1011221A2 75 broken channels----> Pending 77 2025-10-15 10:33:55.040543 GSI
M1UL1B3010093A2 Ohmic behaviour 77 2025-10-15 10:40:05.657495 GSI
M8UR1B2011222B2 Fluctuating current 77 2025-10-15 11:07:24.327159 GSI
M8UR3T2011222A2 75 broken channels 77 2025-10-15 11:32:53.248025 GSI
M8UR1T1011221A2 75 broken channels 77 2025-10-15 11:33:51.171395 GSI
M7DR4T1000221B2 Correction 7 2025-10-16 08:42:21.360383 GSI
M3UL3T0010120B2 Fix doublet in Db 7 2025-10-16 08:52:53.029757 GSI
M8UR7T1011261A2 FEBs get inverted and this module is in GSI 77 2025-10-20 13:43:04.780242 GSI
M7UR6T1011261A2 FEBs get inverted and this module is in GSI 77 2025-10-20 13:44:09.391066 GSI
M1UL1B0010090A5 A small asymmetric current at EOF 77 2025-10-28 14:17:26.299091 GSI
M1UL1B1010091A5 A small asymmetric current at EOF 77 2025-10-28 14:17:34.878175 GSI
M1UL3B1010101A5 Small asymmetric current at EOL 77 2025-10-28 14:24:06.181234 GSI
M1UL3B3010103A2 Solder tin over an uplink capacitor 77 2025-10-28 14:24:44.892602 GSI
M7DR2B4000224A2 Slow breakdown at 125V. It reaches EOL (200V) with current 2.5microA. 77 2025-10-28 14:31:34.909223 GSI
M3UL5B1110141A2 Module created 76 2025-11-04 13:47:50.379564 GSI
M3UL5B0110140A2 Module created 76 2025-11-04 13:48:53.32815 GSI
M8UR3B0111220B2 Module created 76 2025-11-04 13:50:17.680852 GSI
M7DL1B3101223B2 Module created 76 2025-11-04 13:50:54.924853 GSI
M5DR0T2000562B2 Sensor recovered and tested 5 2025-11-06 08:33:23.832405 GSI
M5DR6T0000190B2 Sensor recovered and tested 5 2025-11-06 08:37:44.652873 GSI
M3UL5B0010140A2 Sensor recovered and tested 5 2025-11-06 08:38:03.289414 GSI
M4DR5T0000180B2 Sensor recovered and tested 5 2025-11-06 08:38:29.357483 GSI
M3UL5B1010141A2 Sensor recovered and tested 5 2025-11-06 08:38:50.870647 GSI
M6UR1T2011352A2 ASIC missing, waiting for spare cable 5 2025-11-06 08:50:11.822863 GSI
M4UL4T2010322B2 Sensor recovered and tested 5 2025-11-06 09:34:02.628558 GSI
M0DR1T1000091B5 Sensor recovered and tested 5 2025-11-06 10:14:54.983038 GSI
M5DR2T1000161B2 Sensor recovered and tested 5 2025-11-06 10:40:53.106516 GSI
M2DL2T3001123A2 Soft breakdown at 350v 1 2025-11-11 10:56:05.073049 GSI
M2DL0T2001532A2 Asymmetric current 1 2025-11-11 10:56:57.317457 GSI
M2DL0T1001531A2 Current raised after 200V 1 2025-11-11 10:57:44.789124 GSI
M8UL0B1010601A2 Grade B: Breakdown at 380 V 1 2025-11-12 07:05:46.316522 GSI
M3DR4B3000133A2 Module B3 high resitance 9000 Ohm HV Ground to Ground. Fixed by Ralf. 7 2025-11-19 14:44:07.594637 GSI
M8UL0B1010601A2 IV: brekdown at ~420 V. Reached 500 V at 4.5 uA after long Biasing. Desided to be used. 7 2025-11-19 14:47:02.208951 GSI
M4UL0B2010552A2 IV: rising current at 490 before Ladder assembly (3.3 uA) 7 2025-11-19 16:06:14.136834 GSI
M4UL0B2010552A2 IV after Ladder assembly: 10 uA at 410 V 7 2025-11-19 16:06:53.685353 GSI
M4UL0B2010552A2 IV: after long biasing: 8 uA at 500 V. Decided to use on Ladder (01.10.2025) 7 2025-11-19 16:10:16.411249 GSI
M7DR0B0000600A2 49 broken channels (14 on n-side and 35 on p-side) 77 2025-12-02 15:04:29.180012 GSI
M7DR0B2000602A2 51 broken channels (38 on n-side and 13 on p-side) 77 2025-12-02 15:05:12.386555 GSI
M7DR4T2000222B2 35 broken channels(8 on n-side and 27 on p-side) 77 2025-12-02 15:06:56.556704 GSI
M7UR4B0011390B2 39 broken channels 77 2025-12-02 15:09:50.03627 GSI
M7DR4B4000224A2 57 broken channels (14 on n-side and 43 on p-side) 77 2025-12-02 15:10:47.058113 GSI
M0DL0T0001500A5 A spike at 450V but IV continues to 500V 42 2025-12-09 10:59:42.61193 GSI
M1UL3T1010101B5 asymmetric current 42 2025-12-09 11:01:20.313123 GSI
M1UL3T2010102B5 Breakdown at 320V -> Resolved 42 2025-12-09 11:01:50.316018 GSI
M1UL3B2010102A5 Sharp breakdown at 475V -> Resolved 42 2025-12-09 11:02:23.480269 GSI
M1UL3T2010102B5 High ENC noise/ Broken HV filter capacitor 42 2025-12-09 11:07:43.714513 GSI
M1UL3T1010101B5 Breakdown at 370 V. Stored in Binder at 40 C for 72 hours // Breakdown at 460V. 42 2025-12-09 11:08:18.710501 GSI
M1UL3B2010102A5 Soft breakdown at 410 V // Again soft BD at 470V 42 2025-12-09 11:09:08.207463 GSI
M2UL2T3010283B2 28 broken channels (22 of them on ASIC HW_3 p-side) 42 2025-12-09 11:15:02.294761 GSI
M2DL0B2001532B2 54 broken channels 42 2025-12-09 11:19:55.738304 GSI
M2DL2T0001120A2 Slow breakdown at 450V > dry out after calibration and recovered 42 2025-12-09 11:27:43.45377 GSI
M2DL2T2001122A2 Early breakdown -> fixed after dry out 42 2025-12-09 11:28:16.940718 GSI
M2DL2T4001124A2 66 broken channels (60 of them on the ASIC HW_0 n-side) 42 2025-12-09 11:28:48.253686 GSI
M4UL0B2010552A2 Breakdown at 460V, current start raising till breakdown 42 2025-12-09 11:35:52.150447 GSI
M7DR0B1000601A2 Breakown at 400V -> recovered after dry out 42 2025-12-09 11:52:51.692482 GSI
M8UR1T1011221A2 It was decided (CJS) to use the Module as is. Status changed to test passed. 4 2025-12-10 10:49:56.370485 GSI
M5DL1B1001161B2 Removed from Ladder; To be used 7 2025-12-18 14:46:47.067589 GSI
M5DL1B2001162B2 Removed from Ladder; To be used 7 2025-12-18 14:48:30.036551 GSI
M5DL1B3001163B2 Removed from Ladder; To be used 7 2025-12-18 14:48:45.039711 GSI
M5DL1B4001164B2 Removed from Ladder; To be used 7 2025-12-18 14:48:53.491093 GSI
M4UL0T1010551B2 Removed from Ladder; To be used 7 2025-12-18 14:50:45.661765 GSI
M4UL0T2010552B2 Removed from Ladder; To be used 7 2025-12-18 14:50:54.095844 GSI
M4UL0T3010553B2 Removed from Ladder; To be used 7 2025-12-18 14:51:00.299356 GSI
M4UL0T0010550B2 Removed from Ladder fot further investigation 7 2025-12-18 14:58:18.22913 GSI
M0DR1T1100091B5 Unusal peak at 475V -> solved after dry out. ASIC HW 5 pside has high VDDM of 1611mV 42 2025-12-19 14:42:50.650782 GSI
M2UR3T0011290A2 Assignment changed from KIT to GSI. Oleksandr and Irakli 1 2026-01-09 12:22:25.238908 GSI
M7DL3B2001222B2 small damage noteced on sensor: a broken corner in the inactive rim. But IV curve unchanged, good for ladder assembly 7 2026-01-12 14:42:53.605383 GSI
M7DL3B2001222B2 The damage was already seen during sensor optical inspection (6 October 2020): This corner and also the other corner on the same edge, opposite of the bonding edge, is damaged. 76 2026-01-13 13:48:49.332557 GSI
M0DR1T2000092B2 Slowbreakdown starting at 200V and reaching EOL (500V) at 45 micro A 77 2026-01-13 20:38:26.704161 GSI
M0DL0T2001502A2 Breakdown at 425V 77 2026-01-13 20:44:45.248979 GSI
M1DL1T0001090A2 Ohmic behaviour at 75V and At 500V the cuurent was 2.7 microA 77 2026-01-13 20:47:15.678699 GSI
M1DL1T0001090A2 Ohmic behaviour at 75V and At 500V the current was 2.7 microA 77 2026-01-13 20:47:26.131762 GSI
M1DL5B1001111B5 Asymmetric current observed 77 2026-01-13 20:49:37.005556 GSI
M3UL1B0010120A5 Asymmetric current 77 2026-01-13 21:18:59.707129 GSI
M3UL5B0110140A2 Ohmic behavior 77 2026-01-13 21:27:08.559463 GSI
M3UL5B1110141A2 Ohmic behavior 77 2026-01-13 21:27:42.518504 GSI
M2DL0B2001532B2 54 broken channels 77 2026-01-13 21:34:27.877049 GSI
M2DL2B2001122B2 Slowbreakdown at 175V and current is 2.2 microA at 350V 77 2026-01-13 21:36:47.672124 GSI
M2DL2B4001124B2 ASIC 6 (HW 1) n side, the group3 (every forth channel) of channels don't inject pulses. 77 2026-01-13 21:39:51.107438 GSI
M5DR0T2100562B2 39 broken channels (25 on n-side and 14 on p-side) 77 2026-01-13 21:44:24.496082 GSI
M4UR1T3011313A2 Missing uplinks; needs to be rechecked. 42 2026-01-19 14:09:49.639347 GSI
M7DL5T3001233A2 Missing uplinks, needs to be rechecked 42 2026-01-19 14:10:52.377045 GSI
M7DR2B0000220A2 Missing uplinks, needs to be rechecked 42 2026-01-19 14:11:58.166021 GSI
M3DR0B0000540A2 Missing uplinks, needs to be rechecked 42 2026-01-19 14:12:34.074808 GSI
M7DR2B0000220A2 All uplinks were visible 42 2026-01-19 16:57:39.011521 GSI
M4UR1T3011313A2 All uplinks were visible 42 2026-01-19 16:57:55.499557 GSI
M3DR0B0000540A2 checked by Adrian, ok 75 2026-01-20 11:28:25.2291 GSI
M0DR1B4000094A2 During IV it shows clear ohmic behavior after 170V. Current at EOL is 80 microA. 77 2026-01-20 11:40:46.855211 GSI
M0DL0B2001502B2 No ASIC analog response (ASIC 3, HW 4) on N-side. 77 2026-01-20 11:48:04.314878 GSI
M2DL2B4001124B2 On ASIC 6 (HW 1, n-side), group 3 on every channel is not injecting pulses. And on ASIC 0 (HW 1, p-side), the internal pulse generator appears to be broken. 77 2026-01-20 11:50:59.629702 GSI
M1DL5B1001111B5 ENC pattern observed on ASIC 5 (HW 2, n-side). 77 2026-01-20 11:52:15.490759 GSI
M7DL5T3001233A2 All uplinks are visible 42 2026-01-21 09:32:44.765354 GSI
M8UL0B1010601A2 ASIC HW_6 p-side: Even channels are not responding to the internal pulse generator. Connection check OK. 42 2026-01-22 14:52:43.177848 GSI
M8UL0B2010602A2 ASIC HW_0 n-side: Stuck bit in Vref_p potential 42 2026-01-22 14:53:18.547833 GSI
M8UL0B3010603A2 ASIC HW_0, 4, 7 n-side: missing uplinks 42 2026-01-22 14:54:01.608624 GSI
M6DL0T1001581A2 All Resistances checked and ok! 4 2026-01-23 11:25:40.01266 GSI
M6DL0B1001581B2 All resistans checked and ok! 4 2026-01-23 11:26:17.499846 GSI
M6DL0B2001582B2 ODI cheched and ok 4 2026-01-26 11:36:03.741049 GSI
M6DL0T2001582A2 ODI low, P-side 5 Chanels in different groups, N-side 2 Chanels in different groups 4 2026-01-27 09:55:41.317607 GSI
M8UL4T4010224B2 ODI low, N-side 1 chanel 4 2026-01-27 09:57:49.491284 GSI
M8UL4T1010221B2 ODI low, P-side, ASIC _UL1_N 4 2026-01-27 09:59:50.871019 GSI
M8UL4T4010224B2 ODI low ASIC_UL1_N 4 2026-01-27 10:01:21.286633 GSI
M6DL0T2001582A2 ODI: N-side: 4_1_N, 6_1_N, P-Side: 1_0_N, 3_1_N, 4_0_P, 6_0_P, 7_1_P 4 2026-01-27 10:06:42.510713 GSI
M8UL0B3010603A2 ODI low n-side all channel; p-side 1_0_P, 6_1_P 7 2026-01-27 10:35:24.242411 GSI
M1UR2B1011091B5 Asymmertic current is observed and current diff is 0.1 microA and High VDDM temperature of 1632.4mV 77 2026-01-27 15:38:50.599314 GSI
M1UR2T0011090A5 VDDM is high for HW_ID(0 on n-side and 6 on p-side)->1632.4mV. 77 2026-01-27 15:40:26.893593 GSI
M4UL0T1010551B2 Ohmic behaviour 77 2026-01-27 15:48:14.626155 GSI
M5DL1T3001163A2 ODI: n-side: ASIC2_UL1_n 1.5 kOhm 7 2026-01-28 11:52:00.6749 GSI
M6UL4B3010363A2 Unconnected Vref capacitor in ASIC HW_4 n-side 42 2026-01-29 14:21:43.470897 GSI
M3UL3B4010124A2 P-side: ASIC5_UL0_N has no bond connection to the PCB (solder on PCB bond pad). Oleksandr tries to fix it. 7 2026-01-29 14:41:32.723266 GSI
M3UL3B4010124A2 ODI overflow >60M 7 2026-01-29 14:44:30.212577 GSI
M6UL4T3110363B2 40 broken channels, 22 of them are consecutive odd channels of the ASIC HW_6 p-side 42 2026-01-29 14:56:09.535584 GSI
M5DL1T4001164A2 Rechecked 77 2026-01-29 21:58:44.712468 GSI
M5DL1T3001163A2 Rechecked 77 2026-01-29 21:58:50.389699 GSI
M5DL1B3001163B2 Rechecked 77 2026-01-29 22:03:04.00139 GSI
M5DL1B4001164B2 Rechecked 77 2026-01-29 22:03:07.253055 GSI
M5UR6T1011191A2 Rechecked 77 2026-01-29 22:05:05.990735 GSI
M5UR6T0011190A2 Rechecked 77 2026-01-29 22:05:09.999618 GSI
M5UR6B0011190B2 Rechecked 77 2026-01-29 22:05:13.351743 GSI
M5UR6B1011191B2 Rechecked 77 2026-01-29 22:05:15.979599 GSI
M4UR5T2011332A2 Rechecked 77 2026-01-29 22:07:33.487327 GSI
M4UR5T1011331A2 Rechecked 77 2026-01-29 22:07:37.234662 GSI
M4UR5T0011330A2 Rechecked 77 2026-01-29 22:07:39.902878 GSI
M4UR5B0011330B2 Rechecked 77 2026-01-29 22:07:42.608273 GSI
M4UR5B1011331B2 Rechecked 77 2026-01-29 22:07:45.017982 GSI
M4UR5B2011332B2 Rechecked 77 2026-01-29 22:07:47.421884 GSI
M3UL3T4010124B2 Rechecked 77 2026-01-29 22:09:22.025545 GSI
M3UL3T3010123B2 Rechecked 77 2026-01-29 22:09:24.763493 GSI
M3UL3T2010122B2 Rechecked 77 2026-01-29 22:09:27.573978 GSI
M3UL3T1010121B2 Rechecked 77 2026-01-29 22:09:30.493714 GSI
M3UL3T0010120B2 Rechecked 77 2026-01-29 22:09:37.839654 GSI
M3UL3B0010120A2 Rechecked 77 2026-01-29 22:09:40.199231 GSI
M3UL3B1010121A2 Rechecked 77 2026-01-29 22:09:43.014022 GSI
M3UL3B3010123A2 Rechecked 77 2026-01-29 22:10:15.951538 GSI
M3UL3B4010124A2 Rechecked 77 2026-01-29 22:10:20.420898 GSI
M3UL3B4010124A2 Rechecked => One capacitor is not bonded properly 77 2026-01-29 22:11:42.829737 GSI
M3UL3B4010124A2 CORRECTION 7 2026-01-30 08:48:22.779567 GSI
M4UR1T1011311A2 ODI checked, all ok! 4 2026-01-30 10:10:24.814909 GSI
M4UR1B1011311B2 ODI ok. 4 2026-01-30 10:11:28.447149 GSI
M3DR6T1000151B2 ODI ok! 4 2026-01-30 10:14:31.201999 GSI
M3DR6T0000150B2 ODI ok 4 2026-01-30 10:14:52.227009 GSI
M3DR6B0100150A2 ODI ok 4 2026-01-30 10:15:08.483163 GSI
M3DR6B1000151A2 ODI ok 4 2026-01-30 10:15:24.936765 GSI
M2DL2T1001121A2 Retested 77 2026-02-02 16:27:07.335458 GSI
M3UL3B3010123A2 Retested 77 2026-02-02 16:28:07.195317 GSI
M2DL0T3001533A2 Retested 77 2026-02-02 16:29:20.53783 GSI
M8UL2T4010224B2 Retested 77 2026-02-02 16:31:18.1513 GSI
M8UL2T3010223B2 Retested 77 2026-02-02 16:31:21.767775 GSI
M8UL2T2010222B2 Retested 77 2026-02-02 16:31:26.014773 GSI
M8UL2T1010221B2 Retested 77 2026-02-02 16:31:29.406328 GSI
M8UL2T0010220B2 Retested 77 2026-02-02 16:31:31.876617 GSI
M8UL2B0010220A2 Retested 77 2026-02-02 16:31:34.191065 GSI
M8UL2B1010221A2 Retested 77 2026-02-02 16:31:36.725413 GSI
M8UL2B2010222A2 Retested 77 2026-02-02 16:31:38.991744 GSI
M8UL2B3010223A2 Retested 77 2026-02-02 16:31:41.388982 GSI
M8UL2B4010224A2 Retested 77 2026-02-02 16:31:44.013037 GSI
M8UL6T3010243B2 Retested 77 2026-02-02 16:32:27.391426 GSI
M8UL6T2010242B2 Retested 77 2026-02-02 16:32:36.211782 GSI
M8UL6T1010241B2 Retested 77 2026-02-02 16:32:41.286077 GSI
M8UL6T0010240B2 Retested 77 2026-02-02 16:32:45.939517 GSI
M8UL6B0010240A2 Retested (impedance corresponding to few capacitors are ~1.6kohm) 77 2026-02-02 16:33:39.834475 GSI
M8UL6B1010241A2 Retested 77 2026-02-02 16:33:53.415308 GSI
M8UL6B2010242A2 Retested ( impedance <1kOhm) 77 2026-02-02 16:34:35.402021 GSI
M8UL4T1010221B2 Retested 77 2026-02-02 16:36:05.007451 GSI
M8UL4B1010221A2 Retested 77 2026-02-02 16:36:09.477655 GSI
M8UL6B0010240A2 Impedance < 1kOhm 77 2026-02-02 16:41:55.333191 GSI
M8UL6B2010242A2 Impedance ~ 1.6 kOhm (in CL) 77 2026-02-02 16:42:31.910589 GSI
M4UR1T3011313A2 P side, ASIC HW 7: Uplink 0 shows the expected output impedance while uplink 1 shows a low impedance (<1kOhm). Communication is functional via uplink 1. 77 2026-02-02 23:02:36.777041 GSI
M4UR1T3011313A2 ODI low 7 2026-02-03 08:24:44.754109 GSI
M5DL1T3001163A2 CORRECTION 7 2026-02-03 08:30:08.96426 GSI
M4UR1T3011313A2 ODI ok 4 2026-02-03 10:52:36.461661 GSI
M4UR1B3011313B2 ODI ok 4 2026-02-03 10:52:54.162818 GSI
M5UR6T0011190A2 ODI ok 4 2026-02-03 10:53:34.546541 GSI
M7UL1T4010394B2 ODI okay. Ready for assembly 77 2026-02-03 14:57:28.638991 GSI
M7UL1T3010393B2 ODI okay. Ready for assembly 77 2026-02-03 14:57:32.44201 GSI
M7UL1T2010392B2 ODI okay. Ready for assembly 77 2026-02-03 14:57:35.436224 GSI
M7UL1T1010391B2 ODI okay. Ready for assembly 77 2026-02-03 14:57:37.978731 GSI
M7UL1T0010390B2 ODI okay. Ready for assembly 77 2026-02-03 14:57:40.506267 GSI
M7UL1B0110390A2 ODI okay. Ready for assembly 77 2026-02-03 14:57:46.294956 GSI
M7UL1B1010391A2 ODI okay. Ready for assembly 77 2026-02-03 14:57:48.898597 GSI
M7UL1B2010392A2 ODI okay. Ready for assembly 77 2026-02-03 14:57:51.705241 GSI
M7UL1B3010393A2 ODI okay. Ready for assembly 77 2026-02-03 14:57:54.266496 GSI
M7UL1B4010394A2 ODI okay. Ready for assembly 77 2026-02-03 14:57:56.721468 GSI
M8UL2B2010222A2 ODI failed N-side: asic1 UL1_N, asic2 UL1_P and UL0_N, P-side: asic0 UL1_N, asic1 UL1_P, asic 2 UL1_N 75 2026-02-04 07:17:48.078883 GSI
M5DL1T4001164A2 ODI is okay 77 2026-02-04 10:50:16.463471 GSI
M5DL1B4001164B2 ODI is okay 77 2026-02-04 10:52:35.973763 GSI
M5UR6T1011191A2 ODI is okay 77 2026-02-04 10:54:07.927907 GSI
M5UR6B0011190B2 ODI is okay 77 2026-02-04 10:56:07.927651 GSI
M5UR6B1011191B2 ODI is okey 77 2026-02-04 10:57:25.111415 GSI
M4UR5T2011332A2 ODI is okay 77 2026-02-04 11:01:26.672216 GSI
M4UR5T1011331A2 ODI is okay 77 2026-02-04 11:01:57.225992 GSI
M4UR5T0011330A2 ODI is okay 77 2026-02-04 11:02:38.560375 GSI
M4UR5B0011330B2 ODI is okay 77 2026-02-04 11:03:05.840105 GSI
M4UR5B1011331B2 ODI is okay 77 2026-02-04 11:03:30.263564 GSI
M4UR5B2011332B2 ODI is okay 77 2026-02-04 11:04:00.424516 GSI
M3UL3T4010124B2 ODI is okay 77 2026-02-04 11:09:30.180863 GSI
M3UL3T3010123B2 ODI is okay 77 2026-02-04 11:10:01.553192 GSI
M3UL3T2010122B2 ODI is okay 77 2026-02-04 11:10:27.771988 GSI
M3UL3T1010121B2 ODI is okay 77 2026-02-04 11:10:52.253651 GSI
M3UL3T0010120B2 ODI is okay 77 2026-02-04 11:11:31.811663 GSI
M3UL3B0010120A2 ODI is okay 77 2026-02-04 11:12:01.129468 GSI
M3UL3B1010121A2 ODI is okay 77 2026-02-04 11:12:28.049368 GSI
M3UL3B3010123A2 ODI is okay 77 2026-02-04 11:13:00.851778 GSI
M8UL6T3010243B2 ODI is okay 77 2026-02-04 11:13:40.928223 GSI
M8UL6T2010242B2 ODI is okay 77 2026-02-04 11:14:55.52895 GSI
M8UL6T1010241B2 ODI is okay 77 2026-02-04 11:15:22.917462 GSI
M8UL6T0010240B2 ODI is okay 77 2026-02-04 11:15:51.116826 GSI
M8UL6B1010241A2 ODI is okay 77 2026-02-04 11:16:33.916776 GSI
M8UL6B3010243A2 ODI is okay 77 2026-02-04 11:17:11.46365 GSI
M8UL2T4010224B2 ODI is okay 77 2026-02-04 11:17:56.474633 GSI
M8UL2T3010223B2 ODI is okay 77 2026-02-04 11:18:35.599358 GSI
M8UL2T3010223B2 Sorry for previous comment. Corrected : Low ODI (1.7kohm, HW_ID 1, UL 0) 77 2026-02-04 11:21:04.159979 GSI
M8UL2T2010222B2 ODI is okay 77 2026-02-04 11:22:09.839158 GSI
M8UL2T1010221B2 ODI is okay 77 2026-02-04 11:22:47.350415 GSI
M8UL2T0010220B2 ODI is okay 77 2026-02-04 11:23:19.140212 GSI
M8UL2B4010224A2 ODI is okay 77 2026-02-04 11:23:52.485498 GSI
M8UL2T2010222B2 Sorry for previous comments. Corrected: Low ODI (1.8kohms, both uplinks, HW_ID 6) 77 2026-02-04 11:34:37.325478 GSI
M8UL2B0010220A2 Low ODI (1.8 kohms, UL 0, HW_ID 0) 77 2026-02-04 11:36:43.632245 GSI
M8UL2B1010221A2 Low ODI (1.6 kohms, UL 0, HW_ID 0) 77 2026-02-04 11:38:45.503578 GSI
M8UL2B3010223A2 Low ODI (1.6 kohms, HW_ID 0, UL 0) 77 2026-02-04 11:42:38.27662 GSI
M8UL6B0010240A2 ODI failed (uplink 0 (0.8kohms)->HW_ID 0), uplink 0(0.6kohms) -> HW_ID 7, uplink 1 (both lines: 0.5kohms and 2.7kohms)-> HW_ID 7 77 2026-02-04 11:47:39.63863 GSI
M0DL0T2001502A2 Slow breakdown at 425V, desired grade is A (500V). Current at EOL is 42microA. 77 2026-02-05 22:37:09.712388 GSI
M5DL1T0101160A2 ODI all ok 4 2026-02-12 13:55:11.142907 GSI
M0DL0T2001502A2 Slow breakdown at 425V, desired grade is A (500V). Current at EOL is 42microA. 77 2026-02-05 22:37:21.023188 GSI
M0DL0T0001500A5 A spike at 450V but IV continues to 500V. 77 2026-02-05 22:38:39.103825 GSI
M5UR0T3011563A2 ODI tested, one defect but it is uplink 1 which is not needed 75 2026-02-12 11:17:12.044779 GSI
M5UR0B2011562B2 ODI failed ASIC6_UL0_P, ASIC6_UL0_N 75 2026-02-12 11:40:50.640982 GSI
M5UR0B2011562B2 ODI failed on FEB-A ASIC6_UL0_P, ASIC6_UL0_N 75 2026-02-12 11:41:40.708705 GSI
M5DR2T3000163B2 ODI failed on FEB-A: ASIC4_UL0_P, ASIC4_UL0_N 75 2026-02-12 11:43:53.054044 GSI
M5DR2T3000163B2 ODI failed on FEB-A: ASIC4_UL0_P, ASIC4_UL0_N 75 2026-02-12 11:45:59.568982 GSI
M5DR2T2000162B2 ODI failed on FEB-A: ASIC1_UL0_N, ASIC4_UL1_N, ASIC6_UL1_N 75 2026-02-12 11:48:38.343048 GSI
M5DR2T2000162B2 ODI failed on FEB-A: ASIC1_UL0_N, ASIC4_UL1_N, ASIC6_UL1_N but only ASIC 1 needs replacement 75 2026-02-12 11:50:52.107343 GSI
M8UL4T1010221B2 ODI failed on FEB-B: ASIC6UL0_P only one chip needs replacement 75 2026-02-12 11:52:41.668261 GSI
M8UL4T4010224B2 ODI failed on FEB-A: ASIC0_UL1_, N but it is uplink 1, only uplink 0 needed: 75 2026-02-12 11:55:01.885173 GSI
M2DL0B1001531B2 many broken channels, spare cable ordered for one chip, decide later whether to replace chip 75 2026-02-12 12:08:49.81798 GSI
M5UR0B2011562B2 ODI failed, FEB A: ASIC6_UL0_P, ASIC6_UL0P 4 2026-02-12 13:00:56.443416 GSI
M5UR0B1011561B2 ODI all ok 4 2026-02-12 13:01:44.495514 GSI
M5UR0T3011563A2 ODI all ok 4 2026-02-12 13:03:16.710528 GSI
M5UR0T2011562A2 ODI all ok 4 2026-02-12 13:04:12.580659 GSI
M5UR0T1011561A2 ODI all ok 4 2026-02-12 13:07:17.004328 GSI
M5UR0T0011560A2 ODI all ok 4 2026-02-12 13:07:28.152602 GSI
M6UR3T3011363A2 ODI all ok 75 2026-02-12 13:08:12.632758 GSI
M5UR0B0011560B2 ODI all ok 4 2026-02-12 13:08:36.751815 GSI
M5UR0B1011561B2 ODI all ok 4 2026-02-12 13:08:43.096822 GSI
M5UR0B2011562B2 ODI all ok 4 2026-02-12 13:08:54.439365 GSI
M6UR3T2011362A2 ODI all ok 75 2026-02-12 13:09:11.837912 GSI
M6UR3T1011361A2 ODI all ok 75 2026-02-12 13:09:54.913726 GSI
M6UR3T0011360A2 ODI all ok 75 2026-02-12 13:10:12.863799 GSI
M5UR0B2011562B2 ODI Not OK!!! see status 13:00 !! 4 2026-02-12 13:10:17.523121 GSI
M6UR3B0011360B2 ODI all ok 75 2026-02-12 13:10:33.091125 GSI
M6UR3B1011361B2 ODI all ok 75 2026-02-12 13:10:52.520524 GSI
M6UR3B2011362B2 ODI all ok 75 2026-02-12 13:11:09.698524 GSI
M6UR3B3011363B2 ODSI all ok 75 2026-02-12 13:11:29.831842 GSI
M5DR2T4000164B2 ODI all ok 4 2026-02-12 13:11:42.535647 GSI
M5DR2T1100161B2 ODI all ok 4 2026-02-12 13:11:53.725825 GSI
M5DR2T0000160B2 ODI all ok 4 2026-02-12 13:12:08.412081 GSI
M5DR2T0000160B2 ODI all ok 4 2026-02-12 13:12:15.106646 GSI
M5DR2B0000160A2 ODI all ok 4 2026-02-12 13:13:10.9636 GSI
M5DR2B2000162A2 ODI all ok 4 2026-02-12 13:13:16.68262 GSI
M5DR2B2000162A2 ODI all ok 4 2026-02-12 13:13:19.652205 GSI
M5DR2B3000163A2 ODI all ok 4 2026-02-12 13:13:21.919941 GSI
M5DR6T1000191B2 ODI all ok 75 2026-02-12 13:13:23.865556 GSI
M5DR2B4000164A2 ODI all ok 4 2026-02-12 13:13:24.162599 GSI
M5DR6B0000190A2 ODI all ok 75 2026-02-12 13:13:44.107749 GSI
M5DR6B1000191A2 ODI all ok 75 2026-02-12 13:13:59.570508 GSI
M5DR0T3000563B2 ODI all ok 75 2026-02-12 13:14:39.2922 GSI
M5DR0T1000561B2 ODI all ok 75 2026-02-12 13:15:02.117074 GSI
M5DR0T0000560B2 ODI all ok 75 2026-02-12 13:15:25.219121 GSI
M5DR0B0000560A2 ODI all ok 75 2026-02-12 13:15:41.875853 GSI
M5DR0B1000561A2 ODI all ok 75 2026-02-12 13:16:03.327791 GSI
M5DR0B2000562A2 ODI all ok 75 2026-02-12 13:16:18.370672 GSI
M6UR5T2011372A2 ODI all ok 4 2026-02-12 13:16:22.594096 GSI
M6UR5T1011371A2 ODI all ok 4 2026-02-12 13:16:26.07309 GSI
M6UR5T0011370A2 ODI all ok 4 2026-02-12 13:16:30.469034 GSI
M6UR5B0011370B2 ODI all ok 4 2026-02-12 13:16:32.718889 GSI
M5DR0B3000563A2 ODI all ok 75 2026-02-12 13:16:34.581517 GSI
M6UR5B1011371B2 ODI all ok 4 2026-02-12 13:16:35.09596 GSI
M4DR1T4000164B2 ODI all ok 4 2026-02-12 13:25:10.970558 GSI
M4DR1T3000163B2 ODI all ok 4 2026-02-12 13:25:13.485546 GSI
M4DR1T2000162B2 ODI all ok 4 2026-02-12 13:25:15.559814 GSI
M4DR1T1000161B2 ODI all ok 4 2026-02-12 13:25:17.747725 GSI
M4DR1T0000160B2 ODI all ok 4 2026-02-12 13:25:19.808532 GSI
M4DR1B0000160A2 ODI all ok 4 2026-02-12 13:25:24.021199 GSI
M4DR1B1000161A2 ODI all ok 4 2026-02-12 13:25:29.441301 GSI
M4DR1B2000162A2 ODI all ok 4 2026-02-12 13:25:33.582147 GSI
M4DR1B3000163A2 ODI all ok 4 2026-02-12 13:25:35.772854 GSI
M4DR1B4000164A2 ODI all ok 4 2026-02-12 13:25:37.696334 GSI
M4DR3T3000173B2 ODI all ok 4 2026-02-12 13:26:32.757714 GSI
M4DR3T2000172B2 ODI all ok 4 2026-02-12 13:26:36.842659 GSI
M4DR3T1000171B2 ODI all ok 4 2026-02-12 13:26:39.145446 GSI
M4DR3T0000170B2 ODI all ok 4 2026-02-12 13:26:41.006626 GSI
M4DR3B0000170A2 ODI all ok 4 2026-02-12 13:26:43.019384 GSI
M4DR3B1000171A2 ODI all ok 4 2026-02-12 13:26:45.376862 GSI
M4DR3B2000172A2 ODI all ok 4 2026-02-12 13:26:47.303475 GSI
M4DR3B3000173A2 ODI all ok 4 2026-02-12 13:26:49.451577 GSI
M2DL4T3001133A2 ODI all ok 4 2026-02-12 13:43:07.227525 GSI
M2DL4T2001132A2 ODI all ok 4 2026-02-12 13:43:10.884697 GSI
M2DL4B3001133B2 ODI all ok 4 2026-02-12 13:43:29.228789 GSI
M2DL4B2001132B2 ODI all ok 4 2026-02-12 13:43:31.552102 GSI
M2DL4B2001132B2 ODI all ok 4 2026-02-12 13:43:33.888235 GSI
M2DL4T1001131A2 ODI all ok 4 2026-02-12 13:43:46.281227 GSI
M2DL4T0001130A2 ODI all ok 4 2026-02-12 13:43:48.332545 GSI
M2DL4B0001130B2 ODI all ok 4 2026-02-12 13:43:50.666699 GSI
M2DL4B1001131B2 ODI all ok 4 2026-02-12 13:43:52.275393 GSI
M5DL1T1101161A2 ODI all ok 4 2026-02-12 13:47:15.304449 GSI
M5DL1T2101162A2 ODI all ok 4 2026-02-12 13:47:21.523801 GSI
M5DL1T4001164A2 ODI all ok 4 2026-02-12 13:47:23.621741 GSI
M5DL1B1001161B2 ODI all ok 4 2026-02-12 13:47:28.149897 GSI
M5DL1B2001162B2 ODI all ok 4 2026-02-12 13:47:30.198133 GSI
M5DL1B4001164B2 ODI all ok 4 2026-02-12 13:47:32.001014 GSI
M5DL1B3001163B2 ODI all ok 4 2026-02-12 13:47:44.282258 GSI
M5DL1T0101160A2 ODI all ok 4 2026-02-12 13:55:07.371257 GSI
M7UL1T3010393B2 ODI all ok 4 2026-02-12 13:58:33.637019 GSI
M7UL1T2010392B2 ODI all ok 4 2026-02-12 13:58:37.095846 GSI
M7UL1T1010391B2 ODI all ok 4 2026-02-12 13:58:40.144294 GSI
M7UL1T0010390B2 ODI all ok 4 2026-02-12 13:58:42.268605 GSI
M7UL1B0110390A2 ODI all ok 4 2026-02-12 13:58:45.577876 GSI
M7UL1B1010391A2 ODI all ok 4 2026-02-12 13:58:47.740034 GSI
M7UL1B2010392A2 ODI all ok 4 2026-02-12 13:58:49.693822 GSI
M7UL1B3010393A2 ODI all ok 4 2026-02-12 13:58:51.565308 GSI
M7UL1B0110390A2 ODI all ok 4 2026-02-12 14:06:15.159166 GSI
M7UL1T0010390B2 ODI all ok 4 2026-02-12 14:06:18.840982 GSI
M5UR4T3011173A2 ODI all ok 4 2026-02-12 14:44:26.5325 GSI
M5UR4T2011172A2 ODI all ok 4 2026-02-12 14:44:28.88171 GSI
M5UR4T1011171A2 ODI all ok 4 2026-02-12 14:44:31.276241 GSI
M5UR4T0011170A2 ODI all ok 4 2026-02-12 14:44:33.927126 GSI
M5UR4B0011170B2 ODI all ok 4 2026-02-12 14:44:36.011851 GSI
M5UR4B1011171B2 ODI all ok 4 2026-02-12 14:44:38.14567 GSI
M5UR4B2011172B2 ODI all ok 4 2026-02-12 14:44:40.00162 GSI
M5UR4B3011173B2 ODI all ok 4 2026-02-12 14:44:41.82157 GSI
M6DL2T4001204A2 ODI all ok 4 2026-02-12 14:45:29.069357 GSI
M6DL2T3001203A2 ODI all ok 4 2026-02-12 14:45:31.641087 GSI
M6DL2T2001202A2 ODI all ok 4 2026-02-12 14:45:33.530458 GSI
M6DL2T1001201A2 ODI all ok 4 2026-02-12 14:45:35.755629 GSI
M6DL2T0001200A2 ODI all ok 4 2026-02-12 14:45:37.445733 GSI
M6DL2B0001200B2 ODI all ok 4 2026-02-12 14:45:41.255828 GSI
M6DL2B1001201B2 ODI all ok 4 2026-02-12 14:45:43.064154 GSI
M6DL2B2001202B2 ODI all ok 4 2026-02-12 14:45:45.102686 GSI
M6DL2B3001203B2 ODI all ok 4 2026-02-12 14:45:47.236579 GSI
M6DL2B4001204B2 ODI all ok 4 2026-02-12 14:45:48.914123 GSI
M5DR4T3000173B2 ODI all okay 77 2026-02-12 15:40:36.095057 GSI
M5DR4T2000172B2 ODI all okay 77 2026-02-12 15:40:39.054487 GSI
M5DR4T1000171B2 ODI all okay 77 2026-02-12 15:40:42.730549 GSI
M5DR4T0000170B2 ODI all okay 77 2026-02-12 15:40:47.07636 GSI
M5DR4B0000170A2 ODI all okay 77 2026-02-12 15:40:50.48022 GSI
M5DR4B1000171A2 ODI all okay 77 2026-02-12 15:40:52.879876 GSI
M5DR4B2000172A2 ODI all okay 77 2026-02-12 15:40:55.184517 GSI
M5DR4B3000173A2 ODI all okay 77 2026-02-12 15:40:57.364176 GSI
M5UR2T4011164A2 ODI all ok 4 2026-02-13 11:03:38.444037 GSI
M5UR2T3011163A2 ODI all ok 4 2026-02-13 11:03:43.424145 GSI
M5UR2T2011162A2 ODI all ok 4 2026-02-13 11:03:47.913757 GSI
M5UR2T1011161A2 ODI failed, FEB A: ASIC0_UL0_N 0,6kOhm 4 2026-02-13 11:04:57.874204 GSI
M5UR2T0011160A2 ODI all ok 4 2026-02-13 11:05:04.940078 GSI
M5UR2B0011160B2 ODI all ok 4 2026-02-13 11:05:13.579467 GSI
M5UR2B2011162B2 ODI all ok 4 2026-02-13 11:06:23.738445 GSI
M5UR2B3011163B2 ODI all ok 4 2026-02-13 11:06:26.382032 GSI
M3UL3B4010124A2 Disconnected uplink bond wire reconnected on ASIC5-UL0_N , module now recovered 81 2026-02-13 12:53:02.994784
M4UL0T0010550B2 Replaced ASIC2, HW-Adr.4, back to be tested 81 2026-02-13 12:55:36.48091
M6DR1T4000204B2 ODI: OL because glue, Alex will remove it, than we look again. 4 2026-02-13 13:54:34.044447 GSI
M6DR1T3000203B2 ODI: OL because glue, Alex will remove it, than we look again. 4 2026-02-13 13:54:37.960577 GSI
M6DR1B0000200A2 ODI: OL because glue, Alex will remove it, than we look again. 4 2026-02-13 13:54:45.260842 GSI
M6DR1T2000202B2 ODI all ok 4 2026-02-13 13:54:55.204482 GSI
M6DR1T1000201B2 ODI all ok 4 2026-02-13 13:54:59.165324 GSI
M6DR1T0000200B2 ODI all ok 4 2026-02-13 13:55:01.976306 GSI
M6DR1B1000201A2 ODI all ok 4 2026-02-13 13:55:05.53213 GSI
M6DR1B2000202A2 ODI all ok 4 2026-02-13 13:55:07.935519 GSI
M6DR1B3000203A2 ODI all ok 4 2026-02-13 13:55:12.144662 GSI
M6DR1B4000204A2 ODI all ok 4 2026-02-13 13:55:13.980459 GSI
M4UR1T4011314A2 ODI all ok 4 2026-02-13 13:58:15.572655 GSI
M4UR1T3011313A2 ODI all ok 4 2026-02-13 13:58:19.385391 GSI
M4UR1T2011312A2 ODI all ok 4 2026-02-13 13:58:21.620221 GSI
M4UR1T1011311A2 ODI all ok 4 2026-02-13 13:58:23.918746 GSI
M4UR1T0011310A2 ODI all ok 4 2026-02-13 13:58:26.549566 GSI
M4UR1B0011310B2 ODI all ok 4 2026-02-13 13:58:28.924037 GSI
M4UR1B2011312B2 ODI all ok 4 2026-02-13 13:58:30.820158 GSI
M4UR1B2011312B2 ODI all ok 4 2026-02-13 13:58:34.650617 GSI
M4UR1B3011313B2 ODI all ok 4 2026-02-13 13:58:36.698545 GSI
M4UR1B4011314B2 ODI all ok 4 2026-02-13 13:58:38.395879 GSI
M6DR1B1000201A2 ODI all ok 4 2026-02-13 14:02:20.607833 GSI
M6DR1T3000203B2 ODI all ok 4 2026-02-13 14:03:13.269652 GSI
M6DR1T4000204B2 ODI all ok 4 2026-02-13 14:03:16.070582 GSI
M7DR2B1000221A2 ODI failed 77 2026-02-13 15:42:09.785931 GSI
M7DR2T4000224B2 ODI all okay 77 2026-02-13 15:42:38.798011 GSI
M7DR2T3000223B2 ODI all okay 77 2026-02-13 15:42:43.459377 GSI
M7DR2T2000222B2 ODI all okay 77 2026-02-13 15:42:46.898963 GSI
M7DR2T1000221B2 ODI all okay 77 2026-02-13 15:42:57.721216 GSI
M7DR2T0000220B2 ODI all okay 77 2026-02-13 15:43:05.294847 GSI
M7DR2B2000222A2 ODI all okay 77 2026-02-13 15:43:10.141497 GSI
M7DR2B3000223A2 ODI all okay 77 2026-02-13 15:43:12.253146 GSI
M7DR2B4000224A2 ODI all okay 77 2026-02-13 15:43:14.410863 GSI
M1UR2T1011091A5 ODI all okay 77 2026-02-13 17:28:24.828276 GSI
M1UR2T0011090A5 ODI all okay 77 2026-02-13 17:28:34.439249 GSI
M1UR2B1011091B5 ODI all okay 77 2026-02-13 17:28:50.31045 GSI
M1UR2B0011090B5 ODI all okay 77 2026-02-13 17:29:01.523819 GSI
M1UR2B3011093B2 ODI all okay 77 2026-02-13 17:29:23.321721 GSI
M1UR2T3011093A2 ODI all okay 77 2026-02-13 17:29:28.156221 GSI
M1UR2T2011092A2 ODI all okay 77 2026-02-13 17:29:43.911451 GSI
M1UR2B2011092B2 ODI all okay 77 2026-02-13 17:29:51.252707 GSI
M7DR2B0000220A2 ODI all okay 77 2026-02-13 17:31:04.760004 GSI
M7DR6B2000242A2 ODI all okay 77 2026-02-13 17:31:28.734255 GSI
M7DR6B2000242A2 Correction, not tested yet 77 2026-02-13 17:35:35.378163 GSI
M7DR6T0000240B2 ODI all ok 77 2026-02-13 17:36:53.629504 GSI
M4UL0T1010551B2 ODI all ok 77 2026-02-13 17:37:29.139876 GSI
M4UL0T2010552B2 ODI all ok 77 2026-02-13 17:37:52.517437 GSI
M4UL0T3010553B2 ODI all ok 77 2026-02-13 17:37:57.893901 GSI
M2DL2B1001121B2 ODI all ok 77 2026-02-13 17:39:04.478782 GSI
M1DL1T0001090A2 ODI all ok 77 2026-02-13 17:40:57.649029 GSI
M1UR0B2011512B2 ODI all ok 77 2026-02-13 17:44:02.884359 GSI
M1UR2T4011094A2 ODI all ok 77 2026-02-13 17:46:25.791454 GSI
M1UR2B4011094B2 ODI all ok 77 2026-02-13 17:46:29.67958 GSI
M0DR3T4000104B2 ODI all ok 77 2026-02-13 17:47:59.344793 GSI
M0DR3B4000104A2 ODI all ok 77 2026-02-13 17:48:05.014972 GSI
M0DR3T3000103B2 ODI all ok 77 2026-02-13 17:48:10.325559 GSI
M0DR3B3000103A2 ODI all ok 77 2026-02-13 17:48:13.333977 GSI
M0DR3T0000100B5 ODI all ok 77 2026-02-13 17:48:18.783972 GSI
M0DR3B0000100A5 ODI all ok 77 2026-02-13 17:48:22.164679 GSI
M1UR0B2011512B2 ODI all ok 77 2026-02-13 17:52:17.852133 GSI
M1UR0B0011510B5 ODI all ok 77 2026-02-13 17:52:53.045036 GSI
M1UR0T0011510A5 ODI all ok 77 2026-02-13 17:53:06.756971 GSI
M1UR0T2011512A2 ODI all ok 77 2026-02-13 17:54:41.400647 GSI
M1UR0T3011513A2 ODI all ok 77 2026-02-13 17:55:05.609162 GSI
M1UR0B3011513B2 ODI all ok 77 2026-02-13 17:55:08.544708 GSI
M2UL2B1010281A2 ODI all ok 77 2026-02-13 17:55:48.290637 GSI
M2UL2B2010282A2 ODI all ok 77 2026-02-13 17:55:51.08792 GSI
M2DL2T3001123A2 ODI all ok 77 2026-02-13 17:56:13.457664 GSI
M2DL2B3001123B2 ODI all ok 77 2026-02-13 17:56:15.919309 GSI
M2DL2T0001120A2 ODI all ok 77 2026-02-13 17:56:26.50917 GSI
M2DL2B0001120B2 ODI all ok 77 2026-02-13 17:56:29.20237 GSI
M2DL2T4001124A2 ODI all ok 77 2026-02-13 17:56:37.244961 GSI
M2DL2B4001124B2 ODI all ok 77 2026-02-13 17:56:39.966489 GSI
M2DL2T2001122A2 ODI all ok 77 2026-02-13 17:56:46.473038 GSI
M2DL2B2001122B2 ODI all ok 77 2026-02-13 17:56:49.513515 GSI
M8UR3B0111220B2 ODI all ok 77 2026-02-13 17:59:04.082309 GSI
M8UR3B2011222B2 ODI all ok 77 2026-02-13 17:59:21.079218 GSI
M8UR3B3011223B2 ODI all ok 77 2026-02-13 17:59:28.807001 GSI
M8UR3B4011224B2 ODI all ok 77 2026-02-13 17:59:31.895647 GSI
M8UR3T3011223A2 ODI all ok 77 2026-02-13 17:59:42.656512 GSI
M8UR3T4011224A2 ODI failed 77 2026-02-13 17:59:54.101425 GSI
M8UR3T0011220A2 ODI all ok 77 2026-02-13 18:00:12.921148 GSI
M8UR3T1011221A2 ODI all ok 77 2026-02-13 18:00:20.277384 GSI
M7DR6T3000243B2 ODI all ok 4 2026-02-16 09:49:11.792694 GSI
M7DR6T2000242B2 ODI all ok 4 2026-02-16 09:49:14.73609 GSI
M7DR6T1000241B2 ODI all ok 4 2026-02-16 09:49:18.560493 GSI
M7DR6B0000240A2 ODI all ok 4 2026-02-16 09:49:23.339011 GSI
M7DR6B1000241A2 ODI all ok 4 2026-02-16 09:49:27.181436 GSI
M7DR6B1000241A2 ODI all ok 4 2026-02-16 09:49:32.842243 GSI
M7DR6B2000242A2 ODI all ok 4 2026-02-16 09:49:35.276234 GSI
M7DR6B3000243A2 ODI all ok 4 2026-02-16 09:49:37.74871 GSI
M7DR2B1000221A2 ODI ok, da ASIC6_UL1_N 0,6kOhm aber es wird nur 1 uplink benoetigt. 4 2026-02-16 09:58:52.376405 GSI
M6UR1T4011354A2 ODI all ok 4 2026-02-16 11:16:42.170694 GSI
M6UR1T1011351A2 ODI all ok 4 2026-02-16 11:16:52.760815 GSI
M6UR1T1011351A2 ODI all ok 4 2026-02-16 11:17:24.142996 GSI
M6UR1T0011350A2 ODI all ok 4 2026-02-16 11:17:29.791156 GSI
M6UR1T0011350A2 ODI all ok 4 2026-02-16 11:17:32.738508 GSI
M6UR1B0011350B2 ODI all ok 4 2026-02-16 11:17:35.489297 GSI
M6UR1B1011351B2 ODI all ok 4 2026-02-16 11:17:37.693261 GSI
M6UR1B2011352B2 ODI all ok 4 2026-02-16 11:17:39.889352 GSI
M6UR1B3011353B2 ODI all ok 4 2026-02-16 11:17:41.594376 GSI
M6UR1B4011354B2 ODI all ok 4 2026-02-16 11:17:43.737965 GSI
M6DR5T2000252B2 ODI all ok 4 2026-02-16 11:19:25.31905 GSI
M6DR5T1000251B2 ODI all ok 4 2026-02-16 11:19:27.492088 GSI
M6DR5T0000250B2 ODI all ok 4 2026-02-16 11:19:29.289763 GSI
M6DR5B0000250A2 ODI all ok 4 2026-02-16 11:19:31.21758 GSI
M6DR5B1000251A2 ODI all ok 4 2026-02-16 11:19:32.860201 GSI
M6DR5B2000252A2 ODI all ok 4 2026-02-16 11:19:34.352796 GSI
M7UR2T4011394A2 ODI all ok 77 2026-02-16 12:23:25.141244 GSI
M7UR2T3011393A2 ODI all ok 77 2026-02-16 12:23:28.72819 GSI
M7UR2T2011392A2 ODI all ok 77 2026-02-16 12:23:30.91271 GSI
M7UR2T1011391A2 ODI all ok 77 2026-02-16 12:23:32.837736 GSI
M7UR2T0011390A2 ODI all ok 77 2026-02-16 12:23:34.42849 GSI
M7UR2B0011390B2 ODI all ok 77 2026-02-16 12:23:36.268171 GSI
M7UR2B1011391B2 ODI all ok 77 2026-02-16 12:23:38.033728 GSI
M7UR2B2011392B2 ODI all ok 77 2026-02-16 12:23:41.011993 GSI
M7UR2B3011393B2 ODI all ok 77 2026-02-16 12:23:43.103716 GSI
M7UR2B4011394B2 ODI all ok 77 2026-02-16 12:23:45.764165 GSI
M0DL0T3001503A2 ODI all ok 4 2026-02-16 13:09:36.622958 GSI
M0DL0T2001502A2 ODI all ok 4 2026-02-16 13:09:38.745964 GSI
M0DL0T1001501A5 ODI all ok 4 2026-02-16 13:09:40.834208 GSI
M0DL0T0001500A5 ODI all ok 4 2026-02-16 13:09:42.824163 GSI
M0DL0B0001500B5 ODI all ok 4 2026-02-16 13:09:47.976781 GSI
M0DL0B1001501B5 ODI all ok 4 2026-02-16 13:09:50.303125 GSI
M0DL0B2001502B2 ODI all ok 4 2026-02-16 13:09:52.093116 GSI
M0DL0B3001503B2 ODI all ok 4 2026-02-16 13:09:53.779013 GSI
M7UL3T2010392B2 ODI all ok 77 2026-02-16 14:05:40.69357 GSI
M7UL3B0010390A2 ODI all ok 77 2026-02-16 14:05:46.245072 GSI
M7UL3T4010394B2 Low ODI (P-side ASIC HW_ID 7, UPLINK 0, 1.7kohms) 77 2026-02-16 14:08:52.060893 GSI
M7UL3T0010390B2 OL ODI (P-side ASIC HW_ID 5, UPLINK 1, one line) 77 2026-02-16 14:11:03.522632 GSI
M5UR0B3011563B2 ODI OK 77 2026-02-16 14:28:08.518235 GSI
M6UR1T3111353A2 ODI all ok 77 2026-02-16 14:34:30.64501 GSI
M6UR1T2011352A2 ODI all ok 77 2026-02-16 14:35:04.623711 GSI
M5UR2B1011161B2 ODI all ok 77 2026-02-16 14:35:45.546778 GSI
M5UR2B4111164B2 ODI all ok 77 2026-02-16 14:36:05.853027 GSI
M5DR6T0100190B2 ODI all ok 77 2026-02-16 14:37:08.428046 GSI
M7UL3T3010393B2 ODI all ok 77 2026-02-16 14:39:32.041008 GSI
M7UL3T2010392B2 ODI all ok 77 2026-02-16 14:40:05.584324 GSI
M7UL3T1010391B2 ODI all ok 77 2026-02-16 14:40:11.908814 GSI
M7UL3B0010390A2 ODI all ok 77 2026-02-16 14:40:25.63361 GSI
M7UL3B1010391A2 ODI all ok 77 2026-02-16 14:40:29.095589 GSI
M7UL3B2110392A2 ODI all ok 77 2026-02-16 14:40:31.387239 GSI
M7UL3B3010393A2 ODI all ok 77 2026-02-16 14:40:33.450585 GSI
M7UL3B4010394A2 ODI all ok 77 2026-02-16 14:40:35.146439 GSI
M4DR5T0100180B2 ODI all ok 77 2026-02-16 15:58:58.802491 GSI
M4DR5T2000182B2 ODI all ok 77 2026-02-16 16:02:33.200421 GSI
M4DR5B0000180A2 ODI all ok 77 2026-02-16 16:02:38.596813 GSI
M4DR5B1000181A2 ODI all ok 77 2026-02-16 16:02:41.220712 GSI
M4DR5B2100182A2 ODI all ok 77 2026-02-16 16:02:43.52634 GSI
M4DR5T1000181B2 Low ODI (N-side: ASIC 3, UL_1, 550Ohms, ASIC 4,5,6,7 mostly < 1kohms), (P-side : ASIC 7, UL_ 0, 1.7kOhms) 77 2026-02-16 16:06:25.206913 GSI
M1UR0T3011513A2 ENC pattern z-strip 77 2026-02-17 10:06:29.723162 GSI
M0DL2T4001094A2 ODI all OK 80 2026-02-17 10:42:59.189814 GSI
M0DL2T3001093A2 ODI all OK 80 2026-02-17 10:43:13.234642 GSI
M0DL2T2001092A2 ODI all OK 80 2026-02-17 10:43:21.879103 GSI
M0DL2T1001091A5 ODI all OK 80 2026-02-17 10:43:25.669667 GSI
M0DL2T0001090A5 ODI all OK 80 2026-02-17 10:43:28.618966 GSI
M0DL2B0001090B5 ODI all OK 80 2026-02-17 10:43:31.665703 GSI
M0DL2B0001090B5 ODI all OK 80 2026-02-17 10:43:35.985648 GSI
M0DL2B1001091B5 ODI all OK 80 2026-02-17 10:43:39.839655 GSI
M0DL2B2001092B2 ODI all OK 80 2026-02-17 10:43:43.468601 GSI
M0DL2B3001093B2 ODI all OK 80 2026-02-17 10:43:46.056823 GSI
M0DL2B4001094B2 ODI all OK 80 2026-02-17 10:43:48.328428 GSI
M3UL5T2010142B2 ODI all OK 80 2026-02-17 11:27:32.841188 GSI
M3UL5T1010141B2 ODI all OK 80 2026-02-17 11:27:37.075348 GSI
M3UL5T0010140B2 ODI all OK 80 2026-02-17 11:27:39.962708 GSI
M3UL5B0110140A2 ODI all OK 80 2026-02-17 11:27:42.58926 GSI
M3UL5B1110141A2 ODI all OK 80 2026-02-17 11:27:44.735415 GSI
M3UL5B2010142A2 ODI all OK 80 2026-02-17 11:27:47.273557 GSI
M0DR3B2000102A5 ODI is not ok 77 2026-02-17 11:53:44.223109 GSI
M0DR3B2000102A5 The module has been tested for IV and Calibration and it is passed. But ODI is not okay and hence the module is in HL. 77 2026-02-17 11:56:49.296355 GSI
M1DL1T1001091A2 OL because of glob top when ODI measured. But all uplinks were visible during functionality test. 77 2026-02-17 12:03:35.400447 GSI
M8UR1B3011223B2 All ASICs showing impedance 1.4kohms on n-side. While on p-side ASIC_7, UL_1 one line : 1.4kohms and ASIC_5, UL_1 one line : 1.4kohms. 77 2026-02-17 12:11:11.403523 GSI
M3UL1T4010124B2 ODI all ok ( ASIC0_UL1_P 1,5kOhm but just 1 uplink needed) 4 2026-02-17 13:39:01.01746 GSI
M3UL1T3010123B2 ODI all ok 4 2026-02-17 13:39:07.733859 GSI
M3UL1T2010122B2 ODI all ok 4 2026-02-17 13:39:10.791777 GSI
M3UL1T1010121B2 ODI all ok 4 2026-02-17 13:39:13.125687 GSI
M3UL1T0010120B5 ODI all ok 4 2026-02-17 13:39:15.341745 GSI
M3UL1B0010120A5 ODI all ok 4 2026-02-17 13:39:18.104585 GSI
M3UL1B1010121A2 ODI all ok 4 2026-02-17 13:39:19.661078 GSI
M3UL1B2010122A2 ODI all ok 4 2026-02-17 13:39:21.382941 GSI
M3UL1B3010123A2 ODI all ok 4 2026-02-17 13:39:22.927228 GSI
M3UL1B4010124A2 ODI all ok 4 2026-02-17 13:39:24.863502 GSI
M1UL3T4010104B2 ODI all ok 4 2026-02-17 13:44:20.25485 GSI
M1UL3T3010103B2 ODI all ok 4 2026-02-17 13:45:51.814608 GSI
M1UL3T1010101B5 ODI all ok 4 2026-02-17 13:53:03.741849 GSI
M1UL3T0010100B5 ODI all ok 4 2026-02-17 13:53:23.469447 GSI
M1UL3B0010100A5 ODI all ok 4 2026-02-17 13:53:28.889017 GSI
M1UL3B1010101A5 ODI all ok 4 2026-02-17 13:53:31.250332 GSI
M1UL3B3010103A2 ODI all ok 4 2026-02-17 13:53:33.169417 GSI
M1UL3B4010104A2 ODI all ok 4 2026-02-17 13:53:35.089736 GSI
M6DR7T0000210B2 ODI all ok 4 2026-02-17 14:25:15.435041 GSI
M6DR7B0000210A2 ODI all ok 4 2026-02-17 14:25:18.64371 GSI
M7UR6T1011261A2 ODI all OK 80 2026-02-17 14:55:44.880833 GSI
M7UR6B1011261B2 ODI all OK 80 2026-02-17 14:55:55.782423 GSI
M7UR6T0011260A2 ODI all OK 80 2026-02-17 15:05:47.699789 GSI
M7UR6T1011261A2 eratum: this module is pending 7 2026-02-17 15:08:22.790791 GSI
M7UR6B0111260B2 Previous comment was wrong 80 2026-02-17 15:08:39.943735 GSI
M7UR6T1011261A2 database time issue!!!!!! 7 2026-02-17 15:09:18.604275 GSI
M7UR6B1011261B2 Previous comment is not correct, ODI not measured yet 80 2026-02-17 15:11:19.536458 GSI
M7UR6B0111260B2 The previous comment was for anorther module. 80 2026-02-17 15:14:54.35906 GSI
M7UL1T4010394B2 ODI all ok 4 2026-02-18 06:46:29.475412 GSI
M7UL1T3010393B2 ODI all ok 4 2026-02-18 06:46:32.475054 GSI
M7UL1T2010392B2 ODI all ok 4 2026-02-18 06:46:34.320091 GSI
M7UL1T1010391B2 ODI all ok 4 2026-02-18 06:46:36.287155 GSI
M7UL1T0010390B2 ODI all ok 4 2026-02-18 06:46:38.898473 GSI
M7UL1B0110390A2 ODI all ok 4 2026-02-18 06:46:41.039375 GSI
M7UL1B1010391A2 ODI all ok 4 2026-02-18 06:46:43.378813 GSI
M7UL1B2010392A2 ODI all ok 4 2026-02-18 06:46:45.346053 GSI
M7UL1B3010393A2 ODI all ok 4 2026-02-18 06:46:46.86504 GSI
M7UL1B4010394A2 ODI all ok 4 2026-02-18 06:46:48.538979 GSI
M6DL2T4001204A2 ODI all ok 4 2026-02-18 06:47:17.576067 GSI
M6DL2T3001203A2 ODI all ok 4 2026-02-18 06:47:19.694765 GSI
M6DL2T2001202A2 ODI all ok 4 2026-02-18 06:47:21.869078 GSI
M6DL2T1001201A2 ODI all ok 4 2026-02-18 06:47:27.031605 GSI
M6DL2T0001200A2 ODI all ok 4 2026-02-18 06:47:29.039681 GSI
M6DL2B0001200B2 ODI all ok 4 2026-02-18 06:47:30.826806 GSI
M6DL2B1001201B2 ODI all ok 4 2026-02-18 06:47:32.759452 GSI
M6DL2B2001202B2 ODI all ok 4 2026-02-18 06:47:38.616268 GSI
M6DL2B3001203B2 ODI all ok 4 2026-02-18 06:47:40.436439 GSI
M6DL2B4001204B2 ODI all ok 4 2026-02-18 06:47:42.213458 GSI
M8UL2T3010223B2 Chip 0 has been replaced, BUT instead of the PSB & PST microcable, a PLB & PLT cable was installed, which is 1-1.5 cm longer. Can we live with this? 5 2026-02-18 09:50:42.285857 GSI
M7UR0B4011594B2 ODI failed, OL ASIC3_UL0_P 4 2026-02-18 11:23:12.922194 GSI
M7UR0B0011590B2 ODIU all ok 4 2026-02-18 11:23:27.975228 GSI
M7UR0T0011590A2 ODI all ok 4 2026-02-18 11:23:38.516261 GSI
M7UR0T1011591A2 ODI all ok 4 2026-02-18 11:23:42.47697 GSI
M7UR0T2011592A2 ODI all ok 4 2026-02-18 11:23:45.062966 GSI
M0DL2T4001094A2 ODI all ok 4 2026-02-18 11:44:12.651444 GSI
M0DL2T3001093A2 ODI all ok 4 2026-02-18 11:44:15.924078 GSI
M0DL2T2001092A2 ODI all ok 4 2026-02-18 11:44:18.640396 GSI
M0DL2T1001091A5 ODI all ok 4 2026-02-18 11:44:20.562817 GSI
M0DL2T0001090A5 ODI all ok 4 2026-02-18 11:44:22.655063 GSI
M0DL2B0001090B5 ODI all ok 4 2026-02-18 11:44:24.609229 GSI
M0DL2B1001091B5 ODI all ok 4 2026-02-18 11:44:26.520654 GSI
M0DL2B2001092B2 ODI all ok 4 2026-02-18 11:44:29.076143 GSI
M0DL2B3001093B2 ODI all ok 4 2026-02-18 11:44:30.922774 GSI
M0DL2B4001094B2 ODI all ok 4 2026-02-18 11:44:32.5871 GSI
M6DR7T0000210B2 ODI all ok 4 2026-02-18 12:50:46.486847 GSI
M6DR7B0000210A2 ODI all ok 4 2026-02-18 12:50:49.322345 GSI
M7UR0B4011594B2 There was a bonding issue with ASIC 3 UL0_P. After removing gloptop and re-bonding everything worked. 5 2026-02-19 09:29:57.804466 GSI
M4UL0T0010550B2 Recovered 16.02.2026 5 2026-02-19 09:32:39.012989 GSI
M8UL2T3010223B2 Recovered 18.02.2026 5 2026-02-19 09:34:17.751269 GSI
M5DL1T3001163A2 Recovered 18.02.2026 5 2026-02-19 09:35:30.360732 GSI
M7UR4T4011394A2 ODI all ok 4 2026-02-19 13:18:09.43179 GSI
M7UR4T3011393A2 ODI all ok 4 2026-02-19 13:18:13.093636 GSI
M7UR4T2011392A2 ODI all ok 4 2026-02-19 13:18:14.986243 GSI
M7UR4T1011391A2 ODI all ok 4 2026-02-19 13:18:16.47712 GSI
M7UR4T0011390A2 ODI all ok 4 2026-02-19 13:18:18.175912 GSI
M7UR4B0011390B2 ODI all ok 4 2026-02-19 13:18:20.526542 GSI
M7UR4B1011391B2 ODI all ok 4 2026-02-19 13:18:22.461876 GSI
M7UR4B2011392B2 ODI all ok 4 2026-02-19 13:18:24.966254 GSI
M7UR4B3111393B2 ODI all ok 4 2026-02-19 13:18:26.56341 GSI
M7UR4B4011394B2 ODI all ok 4 2026-02-19 13:18:28.174402 GSI
M5DR6T1000191B2 ODI all ok 4 2026-02-19 13:21:45.971441 GSI
M5DR6T0100190B2 ODI all ok 4 2026-02-19 13:21:48.451822 GSI
M5DR6B0000190A2 ODI all ok 4 2026-02-19 13:21:50.272525 GSI
M5DR6B1000191A2 ODI all ok 4 2026-02-19 13:21:51.88882 GSI
M4UR5T2011332A2 ODI all ok 4 2026-02-19 13:24:20.623157 GSI
M4UR5T1011331A2 ODI all ok 4 2026-02-19 13:24:23.75224 GSI
M4UR5T0011330A2 ODI all ok 4 2026-02-19 13:24:26.372948 GSI
M4UR5B0011330B2 ODI all ok 4 2026-02-19 13:24:28.29193 GSI
M4UR5B1011331B2 ODI all ok 4 2026-02-19 13:24:30.422801 GSI
M4UR5B2011332B2 ODI all ok 4 2026-02-19 13:24:32.712191 GSI
M4DR1T4000164B2 ODI all ok 4 2026-02-19 13:28:59.398175 GSI
M4DR1T3000163B2 ODI all ok 4 2026-02-19 13:29:04.110594 GSI
M4DR1T2000162B2 ODI all ok 4 2026-02-19 13:29:06.305154 GSI
M4DR1T1000161B2 ODI all ok 4 2026-02-19 13:29:08.503052 GSI
M4DR1T0000160B2 ODI all ok 4 2026-02-19 13:29:10.374188 GSI
M4DR1B0000160A2 ODI all ok 4 2026-02-19 13:29:11.887008 GSI
M4DR1B1000161A2 ODI all ok 4 2026-02-19 13:29:14.164299 GSI
M4DR1B2000162A2 ODI all ok 4 2026-02-19 13:29:15.880776 GSI
M4DR1B3000163A2 ODI all ok 4 2026-02-19 13:29:17.827265 GSI
M4DR1B4000164A2 ODI all ok 4 2026-02-19 13:29:19.563683 GSI
M3UL3T4010124B2 ODI all ok 4 2026-02-19 13:40:05.8298 GSI
M3UL3T3010123B2 ODI all ok 4 2026-02-19 13:40:14.226648 GSI
M3UL3T2010122B2 ODI all ok 4 2026-02-19 13:40:18.447024 GSI
M3UL3T1010121B2 ODI all ok 4 2026-02-19 13:40:20.783063 GSI
M3UL3T0010120B2 ODI all ok 4 2026-02-19 13:40:22.926074 GSI
M3UL3B0010120A2 ODI all ok 4 2026-02-19 13:40:25.043184 GSI
M3UL3B1010121A2 ODI all ok 4 2026-02-19 13:40:27.279262 GSI
M3UL3B3010123A2 ODI all ok 4 2026-02-19 13:40:29.76829 GSI
M6DR3B0000200A2 ODI failed. ASIC1_UL1N_N OL 4 2026-02-19 13:53:38.857353 GSI
M6DR3T1000201B2 ODI all ok 4 2026-02-19 13:55:57.8098 GSI
M6DR3B1000201A2 ODI all ok 4 2026-02-19 13:56:02.623973 GSI
M6DR3T4000204B2 ODI all ok 4 2026-02-19 13:56:34.92657 GSI
M6DR3B4000204A2 ODI all ok 4 2026-02-19 13:56:38.326633 GSI
M6DR3T3000203B2 ODI all ok 4 2026-02-19 13:58:37.577547 GSI
M6DR3B3000203A2 ODI all ok 4 2026-02-19 13:58:40.913899 GSI
M6DR3T0000200B2 ODI all ok 4 2026-02-19 13:59:24.486935 GSI
M6DR3T2000202B2 ODI all ok 4 2026-02-19 14:04:22.118581 GSI
M6DL0B4101584B2 ODI all OK 80 2026-02-19 14:28:41.423223 GSI
M8UR3B1011221B2 ODI all ok 4 2026-02-19 14:34:19.875515 GSI
M8UR3T2011222A2 ODI is okay 83 2026-02-19 16:00:47.28062
M1DL3B4001104B2 ODI is okay 83 2026-02-23 10:38:04.914692
M1DL3T4001104A2 ODI is okay 83 2026-02-23 10:38:30.942474
M1DL3T3001103A2 ODI is okay 83 2026-02-23 10:38:34.902153
M1DL3B0001100B2 ODI is okay 83 2026-02-23 10:38:37.669767
M8UR1T1011221A2 ODI all ok 4 2026-02-23 11:14:37.925163 GSI
M8UR5T4011234A2 ODI all ok 4 2026-02-23 14:00:16.795348 GSI
M8UR5T3011233A2 ODI all ok 4 2026-02-23 14:00:23.108604 GSI
M8UR5T1011231A2 ODI all ok 4 2026-02-23 14:00:25.407093 GSI
M8UR5T0011230A2 ODI all ok 4 2026-02-23 14:00:27.464541 GSI
M8UR5B1011231B2 ODI all ok 4 2026-02-23 14:00:29.185913 GSI
M8UR5B0011230B2 ODI all ok 4 2026-02-23 14:00:33.29756 GSI
M8UR5B2011232B2 ODI all ok 4 2026-02-23 14:00:35.502906 GSI
M8UR5B3011233B2 ODI all ok 4 2026-02-23 14:00:37.387525 GSI
M8UR5B4011234B2 ODI all ok 4 2026-02-23 14:00:39.071401 GSI
M8UR5T2011232A2 ODI failed: N-side: ASIC4_UL1_P OL 4 2026-02-23 14:02:36.977387 GSI
M1DL1B1001091B2 ODI is okay 83 2026-02-23 16:59:28.417621
M1DL1B0001090B2 ODI is okay 83 2026-02-23 17:00:04.153658
M1DL1B3001093B2 ODI is okay 83 2026-02-23 17:05:30.624093
M3UL1T2010122B2 ODI all ok 4 2026-02-24 13:37:22.873599 GSI
M3UL1T1010121B2 ODI all ok 4 2026-02-24 13:37:35.74468 GSI
M3UL1T0010120B5 ODI all ok 4 2026-02-24 13:37:37.540888 GSI
M3UL1B0010120A5 ODI all ok 4 2026-02-24 13:37:39.681949 GSI
M3UL1B1010121A2 ODI all ok 4 2026-02-24 13:37:41.696238 GSI
M3UL1B2010122A2 ODI all ok 4 2026-02-24 13:37:44.955758 GSI
M3UL1B3010123A2 ODI all ok 4 2026-02-24 13:37:50.581471 GSI
M2UL0T3010523B2 ODI all ok 4 2026-02-24 13:38:01.587717 GSI
M2UL0T2010522B2 ODI all ok 4 2026-02-24 13:38:03.953226 GSI
M2UL0T1010521B2 ODI all ok 4 2026-02-24 13:38:05.812896 GSI
M2UL0T0010520B2 ODI all ok 4 2026-02-24 13:38:07.88619 GSI
M2DL2T1001121A2 Failed module because of missing uplinks on N-side. Issue identified on 02.12.2025 and cross-checked by R.Kapell 82 2026-02-24 13:50:35.978457
M2DL2T1001121A2 ODI issue for most of N-side FEB 82 2026-02-24 13:52:22.874248
M2DL2T1001121A2 Erratum: This Module id set to FAILED 7 2026-02-24 14:51:48.104842 GSI
M0DR1B4000094A2 Grade A sensor turned bad to D, in addition the IV curve has funny kink. Ask Oleksandr to resurrect sensor. Rebuild module. 76 2026-02-25 10:27:26.929428 GSI
M0DL0B2001502B2 ASIC3 HW4 on N-side has to be replaced 76 2026-02-25 10:39:56.190101 GSI
M0DL0T2001502A2 central module of grade A required, has high sensor current -- rebuild the module 76 2026-02-25 10:43:53.582695 GSI
M1DL5B1001111B5 replace ASIC 5 HW2 n-side 76 2026-02-25 10:46:16.647101 GSI
M0DR3B2000102A5 ODI HW4 UL4 (2.2 and 1.5 kOhm) --> OK 76 2026-02-25 10:49:50.308275 GSI
M2UL0B1010521A2 ENC pattern (very little) ASIC 0 (HW-7) p-side (z-strip) 77 2026-02-25 11:05:03.572001 GSI
M2UL0B3010523A2 missing filter capacitor ASIC 7 (HW-0) 77 2026-02-25 11:07:21.403157 GSI
M2UL0B3010523A2 ODI is okay 77 2026-02-25 11:07:46.351359 GSI
M3UL1B4010124A2 ODI okay 77 2026-02-25 11:26:18.176247 GSI
M3UL1B4010124A2 ODI all okay 77 2026-02-25 11:37:34.351014 GSI
M1UL1T4010094B2 ODI all ok 4 2026-02-25 11:38:32.939072 GSI
M1UL1T3010093B2 ODI all ok 4 2026-02-25 11:38:35.42441 GSI
M1UL1T4010094B2 ODI all ok 4 2026-02-25 11:38:41.238712 GSI
M1UL1T3010093B2 ODI all ok 4 2026-02-25 11:38:43.749612 GSI
M1UL1T2010092B2 ODI all ok 4 2026-02-25 11:38:45.643582 GSI
M1UL1T1010091B5 ODI all ok 4 2026-02-25 11:38:48.772634 GSI
M1UL1T0010090B5 ODI all ok 4 2026-02-25 11:38:50.697753 GSI
M1UL1B0010090A5 ODI all ok 4 2026-02-25 11:38:52.424216 GSI
M1UL1B1010091A5 ODI all ok 4 2026-02-25 11:38:54.27752 GSI
M1UL1B2010092A2 ODI all ok 4 2026-02-25 11:38:56.046756 GSI
M1UL1B3010093A2 ODI all ok 4 2026-02-25 11:38:57.570939 GSI
M1UL1B4010094A2 ODI all ok 4 2026-02-25 11:38:59.067232 GSI
M4UR3T1011311A2 ODI all ok 4 2026-02-25 11:39:31.793986 GSI
M4UR3T3011313A2 ODI all ok 4 2026-02-25 11:39:34.222821 GSI
M4UR3B1011311B2 ODI all ok 4 2026-02-25 11:39:36.958707 GSI
M4UR3B3011313B2 ODI all ok 4 2026-02-25 11:39:39.445759 GSI
M4UR3T0011310A2 ODI all ok 4 2026-02-25 11:39:49.376488 GSI
M4UR3B0011310B2 ODI failed: (P-Side: ASIC0_UL0_P 11,65kOhm) 4 2026-02-25 11:41:00.111829 GSI
M0DR1T2000092B2 Slowbreakdown starting at 200V and reaching E0L (500V) at 45 micro 77 2026-02-25 11:57:29.517825 GSI
M0DR1B0000090A5 very small asymmetric current 77 2026-02-25 11:59:03.742866 GSI
M0DR1B1000091A5 Very small asymmetric current 77 2026-02-25 12:02:42.319896 GSI
M7DR6T3000243B2 Slow breakdown at 90V. 77 2026-02-25 12:09:04.156618 GSI
M2UL0B0010520A2 Correction : ODI not tested 77 2026-02-25 12:17:33.080491 GSI
M8UR1B3011223B2 Several uplinks (22 out of 32) have low ODI on n-side 77 2026-02-25 12:24:07.97339 GSI
M4UR3T4011314A2 ODI all ok 4 2026-02-25 14:01:51.564158 GSI
M4UR3T2011312A2 ODI all ok 4 2026-02-25 14:02:15.159104 GSI
M4UR3B2011312B2 ODI all ok 4 2026-02-25 14:02:24.034992 GSI
M4UR3B4011314B2 ODI all ok 4 2026-02-25 14:02:26.009985 GSI
M0DR1B4000094A2 adjusted status - for module rebuilding 76 2026-02-25 15:18:52.260394 GSI
M0DR1B4000094A2 reconsidered: send module for long-term IV test. 76 2026-02-25 15:27:45.724318 GSI
M0DR1T2000092B2 send to long-term IV test 76 2026-02-25 15:29:57.007818 GSI
M0DL0T2001502A2 send to long-term IV test 76 2026-02-25 15:32:36.779843 GSI
M0DL0B2001502B2 corrected status - to replace ASIC 76 2026-02-25 15:34:43.369395 GSI
M2DL2T1001121A2 replacement cables available - since 15.01.2026. 76 2026-02-25 15:43:14.41881 GSI
M1DL5B1001111B5 pending - for ASIC exchange 76 2026-02-25 15:50:58.085362 GSI
M8UR3T2011222A2 exchange one or two ASICs, cables to be ordered 76 2026-02-25 15:56:17.1243 GSI
M2DL0T0001530A2 will be fixed by KIT 76 2026-02-25 16:00:26.212291 GSI
M8UL2T2010222B2 Oleksandr to replace one chip 76 2026-02-25 16:08:12.010125 GSI
M4DR5T1000181B2 inspect for solution to ODI 76 2026-02-25 16:14:29.281453 GSI
M7UR6T1011261A2 This module is completely OK as checked by Carmen, this was also clarified 6 months ago but the database not updated! ODI is also OK! 81 2026-02-26 10:33:50.596812
M8UR7T1011261A2 This module was errornously set to pending. It appeared as if FEBs were interchanged but this prooved wrong. Module is completely OK, ODI tested OK, 81 2026-02-26 10:41:26.499506
M1DL1B4001094B2 ODI is okay 83 2026-02-26 10:42:29.583071
M1DL3B1001101B2 ODI is okay 83 2026-02-26 10:44:37.714573
M1DL3B2001102B2 ODI is okay 83 2026-02-26 10:45:36.923651
M7DR4T4000224B2 ODI all OK 80 2026-02-26 10:45:50.003167 GSI
M7DR4T3000223B2 ODI all OK 80 2026-02-26 10:45:55.96708 GSI
M7DR4T2000222B2 ODI all OK 80 2026-02-26 10:46:00.438526 GSI
M7DR4T0000220B2 ODI all OK 80 2026-02-26 10:46:08.466961 GSI
M7DR4B0000220A2 ODI all OK 80 2026-02-26 10:46:14.426989 GSI
M7DR4B2000222A2 ODI all OK 80 2026-02-26 10:46:19.988105 GSI
M7DR4B3000223A2 ODI all OK 80 2026-02-26 10:46:23.61794 GSI
M7DR4B4000224A2 ODI all OK 80 2026-02-26 10:46:26.153098 GSI
M1DL5T0001110A5 ODI all OK 80 2026-02-26 11:16:02.852795 GSI
M1DL5B0001110B5 ODI all OK 80 2026-02-26 11:16:06.214869 GSI
M1DL5T1001111A5 ODI issue, ASIC3_UL4_P is OL, N_Side 80 2026-02-26 11:18:30.542512 GSI
M0DR1T0000090B5 ODI all OK 80 2026-02-26 11:56:52.091479 GSI
M0DR1B0000090A5 ODI all OK 80 2026-02-26 11:56:56.580686 GSI
M0DR1T1100091B5 ODI all OK 80 2026-02-26 11:56:59.052184 GSI
M0DR1B1000091A5 ODI all OK 80 2026-02-26 11:57:01.513083 GSI
M2DL2T1101121A2 Module created 76 2026-02-26 13:14:57.050011 GSI
M5DR2T4000164B2 ODI all ok 4 2026-02-26 13:35:41.189196 GSI
M5DR2B4000164A2 ODI all ok 4 2026-02-26 13:36:34.430308 GSI
M5DR2B3000163A2 ODI all ok 4 2026-02-26 13:36:37.225317 GSI
M5DR2B2000162A2 ODI all ok 4 2026-02-26 13:36:40.946051 GSI
M5DR2B0000160A2 ODI all ok 4 2026-02-26 13:36:43.384234 GSI
M5DR2T0000160B2 ODI all ok 4 2026-02-26 13:37:12.79321 GSI
M5DR2T1100161B2 ODI all ok 4 2026-02-26 13:37:15.818363 GSI
M5DR2T2000162B2 ODI failed 4 2026-02-26 13:37:51.447441 GSI
M5DR2T3000163B2 ODI failed 4 2026-02-26 13:37:56.704814 GSI
M4DR5T2000182B2 ODI all ok 4 2026-02-26 13:39:59.176992 GSI
M4DR5B0000180A2 ODI all ok 4 2026-02-26 13:40:44.093344 GSI
M4DR5B1000181A2 ODI all ok 4 2026-02-26 13:40:46.900954 GSI
M5UR2T2011162A2 ODI all ok 4 2026-02-26 13:43:12.858957 GSI
M5UR2T3011163A2 ODI all ok 4 2026-02-26 13:43:15.589363 GSI
M5UR2T4011164A2 ODI all ok 4 2026-02-26 13:43:18.379738 GSI
M5UR2T0011160A2 ODI all ok 4 2026-02-26 13:43:57.660051 GSI
M5UR2B0011160B2 ODI all ok 4 2026-02-26 13:44:26.481154 GSI
M5UR2B2011162B2 ODI all ok 4 2026-02-26 13:45:03.22207 GSI
M5UR2B3011163B2 ODI all ok 4 2026-02-26 13:45:29.227217 GSI
M5DR0T3000563B2 ODI all ok 4 2026-02-26 13:49:50.056636 GSI
M5DR0T1000561B2 ODI all ok 4 2026-02-26 13:49:53.272126 GSI
M5DR0T0000560B2 ODI all ok 4 2026-02-26 13:49:55.345209 GSI
M5DR0B0000560A2 ODI all ok 4 2026-02-26 13:49:57.350656 GSI
M5DR0B1000561A2 ODI all ok 4 2026-02-26 13:49:59.526394 GSI
M5DR0B2000562A2 ODI all ok 4 2026-02-26 13:50:01.300033 GSI
M5DR0B3000563A2 ODI all ok 4 2026-02-26 13:50:03.400437 GSI
M5UR0T3011563A2 ODI all ok 4 2026-02-26 13:52:40.451508 GSI
M5UR0B1011561B2 ODI all ok 4 2026-02-26 13:53:39.941304 GSI
M5UR0B0011560B2 ODI all ok 4 2026-02-26 13:53:43.603606 GSI
M5UR0T0011560A2 ODI all ok 4 2026-02-26 13:53:45.546941 GSI
M5UR0T1011561A2 ODI all ok 4 2026-02-26 13:53:47.804847 GSI
M5UR0T2011562A2 ODI all ok 4 2026-02-26 13:53:50.855237 GSI
M3DL5T2001142A2 ODI all ok 75 2026-02-26 14:07:18.02635 GSI
M3DL5T1001141A2 ODI all ok 75 2026-02-26 14:08:00.629551 GSI
M3DL5T0001140A2 ODI all ok 75 2026-02-26 14:08:17.16766 GSI
M3DL5B0101140B2 ODI all ok 75 2026-02-26 14:08:32.448856 GSI
M3DL5B1001141B2 ODI all ok 75 2026-02-26 14:08:48.312068 GSI
M3DL5B2001142B2 ODI all ok 75 2026-02-26 14:09:10.296721 GSI
M3DL3T4101124A2 ODI all ok 75 2026-02-26 14:09:31.476459 GSI
M3DL3T3001123A2 ODI all ok 75 2026-02-26 14:09:59.492737 GSI
M3DL3T2001122A2 ODI all ok 75 2026-02-26 14:10:12.832714 GSI
M3DL3T1001121A2 ODI all ok 75 2026-02-26 14:10:27.479403 GSI
M3DL3T0001120A2 ODI all ok 75 2026-02-26 14:10:40.795368 GSI
M3DL3B0001120B2 ODI all ok 75 2026-02-26 14:10:55.210431 GSI
M3DL3B1001121B2 ODI all ok 75 2026-02-26 14:11:08.398801 GSI
M3DL3B2001122B2 ODI all ok 75 2026-02-26 14:11:23.258099 GSI
M3DL3B3001123B2 ODI all ok 75 2026-02-26 14:11:39.920316 GSI
M3DL3B4001124B2 ODI all ok 75 2026-02-26 14:11:52.79234 GSI
M8UL4T4010224B2 ULX (ASIC7_UL0_P&N to UL1_P&N) 5 2026-02-26 15:56:11.295219 GSI
M7DR4T1000221B2 ODI failed, (P-Side, ASIC0_UL0_P, 0,6kOhm, ASIC0_UL0_N, 03.kOhm ) 4 2026-02-27 09:24:23.786484 GSI
M7DR4B1000221A2 ODI all ok 4 2026-02-27 09:24:53.511555 GSI
M3DL1B0001120B2 ODI failed Feb B asic3_UL0_P and asic7_UL0_P both 1,3kOhm 75 2026-02-27 12:41:29.189826 GSI
M3DL1T4001124A2 ODI all ok 75 2026-02-27 12:42:10.220787 GSI
M3DL1T3001123A2 ODI all ok 75 2026-02-27 12:42:50.961492 GSI
M3DL1T2001122A2 ODI all ok 75 2026-02-27 12:43:11.206197 GSI
M3DL1T1001121A2 ODI all ok 75 2026-02-27 12:43:30.019864 GSI
M3DL1T0001120A2 ODI all ok 75 2026-02-27 12:43:50.50854 GSI
M3DL1B1001121B2 ODI all ok 75 2026-02-27 12:44:17.764778 GSI
M3DL1B2001122B2 ODI all ok 75 2026-02-27 12:44:35.192794 GSI
M3DL1B3001123B2 ODI all ok 75 2026-02-27 12:44:51.611996 GSI
M3DL1B4001124B2 ODI all ok 75 2026-02-27 12:45:07.275576 GSI
M0DR1T4000094B2 ODI all ok 4 2026-02-27 12:46:06.177476 GSI
M0DR1T3000093B2 ODI all ok 4 2026-02-27 12:46:09.695082 GSI
M0DR1B2000092A2 ODI all ok 4 2026-02-27 12:46:12.599306 GSI
M0DR1B3000093A2 ODI all ok 4 2026-02-27 12:46:15.512401 GSI
M0DR1T2000092B2 done: long-term IV test 7 2026-03-02 04:55:05.509822 GSI
M0DR1B4000094A2 done: long-term IV test 7 2026-03-02 04:59:13.035734 GSI
M4DL2T4001164A2 ODI all ok 75 2026-03-02 13:07:58.202126 GSI
M4DL2T3001163A2 ODI all ok 75 2026-03-02 13:08:14.007003 GSI
M4DL2T3001163A2 ODI all ok 75 2026-03-02 13:08:24.730303 GSI
M4DL2T1001161A2 ODI all ok 75 2026-03-02 13:08:40.216682 GSI
M4DL2T0001160A2 ODI all ok 75 2026-03-02 13:08:53.623894 GSI
M4DL2B0001160B2 ODI all ok 75 2026-03-02 13:09:06.696774 GSI
M4DL2B1001161B2 ODI all ok 75 2026-03-02 13:09:18.118409 GSI
M4DL2B2001162B2 ODI all ok 75 2026-03-02 13:09:30.139491 GSI
M4DL2B3001163B2 ODI all ok 75 2026-03-02 13:09:42.444107 GSI
M4DL2B4001164B2 ODI all ok 75 2026-03-02 13:09:53.966359 GSI
M4DL2T2001162A2 ODI all ok 75 2026-03-02 13:10:41.970618 GSI
M7DR0T3000603B2 ODI all ok 4 2026-03-02 13:34:27.155513 GSI
M7DR0T2000602B2 ODI all ok 4 2026-03-02 13:34:29.648029 GSI
M7DR0T1000601B2 ODI all ok 4 2026-03-02 13:34:32.788254 GSI
M7DR0T0000600B2 ODI all ok 4 2026-03-02 13:34:34.851447 GSI
M7DR0B0000600A2 ODI all ok 4 2026-03-02 13:34:37.097273 GSI
M7DR0B2000602A2 ODI all ok 4 2026-03-02 13:34:39.630263 GSI
M7DR0B3000603A2 ODI all ok 4 2026-03-02 13:34:41.167236 GSI
M7DR0B1000601A2 ODI all ok 4 2026-03-02 13:35:04.840088 GSI
M2UL2T3010283B2 ODI all ok 4 2026-03-02 13:50:18.238254 GSI
M3DL1B0001120B2 Feb B asic3_UL0_P ampl. 626mV; and asic7_UL0_P ampl. 622mV 75 2026-03-02 14:26:52.423861 GSI
M5DR6B1000191A2 IV-Messung schlecht. (Kratzer auf P-Side, gesehen, aber vorhergehende IV-Messung war ok) Kabel wurden fuer eine weitere Messung separirert, aber IV-Messung trotzdem schlecht. Der Strom geht gleich hoch. 4 2026-03-03 09:18:10.626779 GSI
M6DL0T4001584A2 ODI all ok 4 2026-03-03 10:17:02.84539 GSI
M6DL0T3001583A2 ODI all ok 4 2026-03-03 10:17:17.064134 GSI
M3DR0B0000540A2 FEB B Asic1_UL0P and N: ampl. 344mV 75 2026-03-03 10:37:23.170035 GSI
M3DR0B2000542A2 FEB A: Asic_UL0 P and N: ampl.320mV and Asic3_UL0 N and P ampl. 400mV, onlzy 1 uplink needed, is ok? 75 2026-03-03 10:41:30.446751 GSI
M7UL3T0010390B2 can be used: Only one uplink is needed, which is OK. The second has the problem. 76 2026-03-03 10:48:37.680943 GSI
M0DR1B4000094A2 during biasramp-up current fluctuations are seen from 280 V on . They remain visible in long-term biassing at 300 V and 250V. Fluctuations are by several microamperes on short time scales. 76 2026-03-03 11:18:16.644549 GSI
M8UL6B2010242A2 detail on Anjus finding: HW_ID 1, uplink 0, 1.6 kOhm 81 2026-03-03 11:22:03.058567
M0DR1T2000092B2 long-term biassing shows promising lowering of currents from 20 to 11 microamps over ~42 hours, a second test ~ 20 hours with currents reducing from 20 to 14 microamps. Suggestion to run the long-term test longer, a few days. Needs a dedicated test stand as the current test stand is also needed for single-IV curves during ladder assembly. 76 2026-03-03 11:30:25.464861 GSI
M8UR5T2011232A2 defective uplink not needed in FEB-8-1, thus module passed 81 2026-03-03 12:44:52.650177
M6DR3B0000200A2 UL1N_N not needed in FEB-8-1, thus ODI tested OK, changed status 81 2026-03-03 12:50:32.478735
M8UL6B2010242A2 ODI low 7 2026-03-03 15:59:51.21903 GSI
M1DL1T3001093A2 ODI is Okay 83 2026-03-04 10:30:01.991791
M1DL1T4001094A2 ODI is okay 83 2026-03-04 10:44:51.469755
M3DR0B0000540A2 ODI low 4 2026-03-04 13:55:45.383696 GSI
M3DR0B2000542A2 ODI low 4 2026-03-04 13:56:52.57235 GSI
M4UL2T4110314B2 ODI all ok 4 2026-03-04 14:04:30.313109 GSI
M4UL2T3110313B2 ODI all ok 4 2026-03-04 14:04:34.09424 GSI
M4UL2T2010312B2 ODI all ok 4 2026-03-04 14:04:36.402414 GSI
M4UL2T1010311B2 ODI all ok 4 2026-03-04 14:04:37.870186 GSI
M4UL2T0010310B2 ODI all ok 4 2026-03-04 14:04:40.940828 GSI
M4UL2B0010310A2 ODI all ok 4 2026-03-04 14:04:43.211136 GSI
M4UL2B1010311A2 ODI all ok 4 2026-03-04 14:04:45.40503 GSI
M4UL2B2010312A2 ODI all ok 4 2026-03-04 14:04:47.077343 GSI
M4UL2B3010313A2 ODI all ok 4 2026-03-04 14:04:48.620277 GSI
M4UL2B4010314A2 ODI all ok 4 2026-03-04 14:04:49.901163 GSI
M3DR0T3000543B2 ODI all ok 4 2026-03-04 14:05:24.018792 GSI
M3DR0T2000542B2 ODI all ok 4 2026-03-04 14:05:26.082294 GSI
M3DR0T1000541B2 ODI all ok 4 2026-03-04 14:05:28.695625 GSI
M3DR0T0000540B2 ODI all ok 4 2026-03-04 14:05:31.085769 GSI
M3DR0B1000541A2 ODI all ok 4 2026-03-04 14:05:33.057717 GSI
M3DR0B3000543A2 ODI all ok 4 2026-03-04 14:05:34.595299 GSI
M4UL4T3010323B2 ODI all ok 4 2026-03-04 15:12:39.190264 GSI
M4UL4T2110322B2 ODI all ok 4 2026-03-04 15:12:41.783087 GSI
M4UL4T1010321B2 ODI all ok 4 2026-03-04 15:12:43.583492 GSI
M4UL4T0010320B2 ODI all ok 4 2026-03-04 15:12:45.383234 GSI
M4UL4B0010320A2 ODI all ok 4 2026-03-04 15:12:47.084546 GSI
M4UL4B2010322A2 ODI all ok 4 2026-03-04 15:12:48.976926 GSI
M4UL4B3010323A2 ODI all ok 4 2026-03-04 15:12:50.444565 GSI
M4UL4B1010321A2 ODI all ok 4 2026-03-04 15:13:20.330264 GSI
M3DR0B0000540A2 81 2026-03-04 16:45:18.306956
M5DR6B1000191A2 15 h bias@EoL test done. 7 2026-03-05 06:03:47.531431 GSI
M8UL4T4010224B2 First module with uplink1 connected to uplink0 traces ULX(ASIC7_UL1_P&N to UL0_P&Ntraces), module can be put on ladder but glob top should be added to rework 81 2026-03-05 10:24:18.731123
M1DL3B3001103B2 ASIC 1 (HW 0) p side: groups 2 and 3 of the channels don't inject pulses. 83 2026-03-05 11:15:06.65265
M1DL3T0001100A2 ODI is okay 83 2026-03-05 11:15:28.413439
M1DL3B3001103B2 ODI is okay 83 2026-03-05 11:16:57.595272
M8UL4T4010224B2 ERRATUM to the first finding: ASIC0_UL1_N was not ODI low but ASIC7_UL0_P 7 2026-03-05 11:23:44.615882 GSI
M8UL4T1010221B2 ULX scheduled. 7 2026-03-05 11:30:09.468896 GSI
M7DL5T4001234A2 ODI all ok 4 2026-03-05 11:35:40.910388 GSI
M7DL5T3001233A2 ODI all ok 4 2026-03-05 11:35:43.264952 GSI
M7DL5T2001232A2 ODI all ok 4 2026-03-05 11:35:45.211418 GSI
M7DL5T1001231A2 ODI all ok 4 2026-03-05 11:35:48.460578 GSI
M7DL5T0001230A2 ODI all ok 4 2026-03-05 11:35:50.676987 GSI
M7DL5B0001230B2 ODI all ok 4 2026-03-05 11:35:52.458675 GSI
M7DL5B1001231B2 ODI all ok 4 2026-03-05 11:35:54.416511 GSI
M7DL5B2001232B2 ODI all ok 4 2026-03-05 11:35:56.661543 GSI
M7DL5B3001233B2 ODI all ok 4 2026-03-05 11:35:58.509486 GSI
M7DL5B4001234B2 ODI all ok 4 2026-03-05 11:36:00.012613 GSI
M4DR5T1000181B2 Multiple solutions: ULX scheduled. ASIC exchange scheduled. Usage of UL0 only. 7 2026-03-05 11:41:34.794302 GSI
M5DR2T3000163B2 ULX scheduled. 7 2026-03-05 11:43:25.722678 GSI
M5UR0B2011562B2 ASIC exchange scheduled. 7 2026-03-05 11:44:48.78796 GSI
M5UR2T1011161A2 ULX scheduled. 7 2026-03-05 12:48:19.031728 GSI
M5DR2T2000162B2 multiple solutions: ULX scheduled, Usage of UL0 only. 7 2026-03-05 12:51:02.485088 GSI
M6DL0T2001582A2 multiple solutions: pending decision, ULX scheduled, Usage of UL0 only 7 2026-03-05 12:54:04.555513 GSI
M7UL3T4010394B2 ULX scheduled. 7 2026-03-05 12:55:42.445236 GSI
M7UR6B1011261B2 ODI OL: FEB B Asic3_UL0. ULX scheduled. 7 2026-03-05 12:58:36.048435 GSI
M8UL2B3010223A2 ULX scheduled. 7 2026-03-05 12:59:13.432975 GSI
M8UL2B0010220A2 ULX scheduled. 7 2026-03-05 12:59:55.583961 GSI
M8UL2T2010222B2 ASIC exchange scheduled 7 2026-03-05 13:02:22.392309 GSI
M8UL2B2010222A2 multiple solutions: pending decision ASIC exchange scheduled 7 2026-03-05 13:04:31.68593 GSI
M8UL2B1010221A2 ASIC exchange scheduled 7 2026-03-05 13:06:33.099543 GSI
M8UR7B0011260B2 ODI all ok 4 2026-03-05 13:07:43.553655 GSI
M8UR7T0011260A2 ODI all ok 4 2026-03-05 13:08:20.965614 GSI
M8UR3T4011224A2 multiple solutions: ULX scheduled, Usage of UL0 only, ASIC exchange scheduled. 7 2026-03-05 13:08:21.274712 GSI
M8UR7B1011261B2 ODI all ok 4 2026-03-05 13:08:54.014542 GSI
M8UR1B3011223B2 pending decision 7 2026-03-05 13:13:09.739248 GSI
M0DR3B2000102A5 pending decision 7 2026-03-05 13:17:34.149944 GSI
M8UR1B3011223B2 multiple solutions: FEB exchange scheduled, Usage of UL0 only 7 2026-03-05 13:21:26.630459 GSI
M3DR0B2000542A2 ULX scheduled. 7 2026-03-05 13:27:03.696938 GSI
M4UR3B0011310B2 pending decision: ULX? 7 2026-03-05 13:29:28.435403 GSI
M7DR4T1000221B2 pending decision: ULX? 7 2026-03-05 13:30:47.392693 GSI
M4UL6T1010341B2 ODI all ok 4 2026-03-06 09:43:21.694932 GSI
M4UL6T0110340B2 ODI all ok 4 2026-03-06 09:43:24.246661 GSI
M4UL6B0010340A2 ODI all ok 4 2026-03-06 09:43:25.987457 GSI
M4UL6B1010341A2 ODI all ok 4 2026-03-06 09:43:28.636722 GSI
M4DL6T1001191A2 ODI all ok 4 2026-03-06 11:55:50.291605 GSI
M4DL6T0001190A2 ODI all ok 4 2026-03-06 11:55:54.371106 GSI
M4DL6B0001190B2 ODI all ok 4 2026-03-06 11:55:56.389132 GSI
M4DL6B1001191B2 ODI all ok after soldering (ASIC7_UL0_P, OL) 4 2026-03-06 11:57:15.357962 GSI
M4DL6B1001191B2 ULX 7 2026-03-06 14:11:05.213665 GSI
M5DR6B1000191A2 62 h bias@EoL test done. 7 2026-03-09 05:17:48.17046 GSI
M0DR1T2000092B2 Long term bias@EoL HV test in dedicated test stand started on 6.3. 7 2026-03-09 07:31:25.044389 GSI
M0DL0T2001502A2 done: : long-term IV test 7 2026-03-09 07:32:39.868583 GSI
M5DR2T3000163B2 ULX done, FEB-A: ASIC 4_UL0 3 2026-03-09 08:47:09.445543 GSI
M5DR2T2000162B2 ULX done, FEB-A: ASIC 1_UL0, ASIC6_UL0, ASIC4_UL1 not needed 3 2026-03-09 08:57:50.804774 GSI
M8UL4T1010221B2 ULX done, FEB-B: ASIC6_UL0 3 2026-03-09 09:01:45.687907 GSI
M6DL0T2001582A2 ULX done, FEB-A: ASIC1_UL0, ASIC4_UL0, ASIC6_UL0, ASIC3_UL1 & 7_UL1 not needed 3 2026-03-09 09:06:59.931274 GSI
M1DL1T4001094A2 Globtop on some capacitors removed, remeasured, all ok 3 2026-03-09 09:10:41.705034 GSI
M1DL1B4001094B2 Globtop removed from some capacitors, remeasured, all ok 3 2026-03-09 09:12:41.140195 GSI
M7UR0B3011593B2 ODI all ok 4 2026-03-09 10:01:29.766024 GSI
M7UR0T3011593A2 ODI all ok 4 2026-03-09 10:02:13.788356 GSI
M7UR0T4011594A2 ODI all ok 4 2026-03-09 10:02:29.516004 GSI
M7UR0B1011591B2 ODI all ok 4 2026-03-09 10:02:37.695994 GSI
M7UR0B2011592B2 ODI all ok 4 2026-03-09 10:02:45.658681 GSI
M8UR1B1011221B2 ODI all ok 4 2026-03-09 10:07:06.364067 GSI
M8UR1B0011220B2 ODI all ok 4 2026-03-09 10:07:16.290038 GSI
M8UR1T0011220A2 ODI all ok 4 2026-03-09 10:07:30.004266 GSI
M8UR1T3011223A2 ODI all ok 4 2026-03-09 10:07:36.678643 GSI
M8UR1T4011224A2 ODI all ok 4 2026-03-09 10:07:39.036534 GSI
M2UL2T4010284B2 ODI all ok 4 2026-03-09 10:08:10.996592 GSI
M2UL2T2010282B2 ODI all ok 4 2026-03-09 10:08:30.579397 GSI
M2UL2T1010281B2 ODI all ok 4 2026-03-09 10:08:33.281499 GSI
M2UL2T0010280B2 ODI all ok 4 2026-03-09 10:08:35.514228 GSI
M2UL2B0010280A2 ODI all ok 4 2026-03-09 10:08:52.690036 GSI
M2UL2B3010283A2 ODI all ok 4 2026-03-09 10:08:54.7698 GSI
M2UL2B4010284A2 ODI all ok 4 2026-03-09 10:08:56.646727 GSI
M2DL0B0001530B2 ODI all ok 4 2026-03-09 10:10:43.697696 GSI
M2DL0B3001533B2 ODI all ok 4 2026-03-09 10:10:47.863757 GSI
M2UL0B2010522A2 ODI all ok 4 2026-03-09 10:11:04.140218 GSI
M0DR3T1000101B5 ODI all ok 4 2026-03-09 10:12:09.497365 GSI
M0DR3T2000102B5 ODI all ok 4 2026-03-09 10:12:17.721188 GSI
M0DR3B1000101A5 ODI all ok 4 2026-03-09 10:12:22.275724 GSI
M1UR0T1011511A5 ODI all ok 4 2026-03-09 10:12:57.987458 GSI
M1DL1T2001092A2 ODI all ok 4 2026-03-09 10:13:19.108204 GSI
M6UR5B2011372B2 ODI all ok 4 2026-03-09 10:14:00.273225 GSI
M1DL1T1001091A2 ODI all ok 4 2026-03-09 10:22:14.117303 GSI
M3DR0B0000540A2 ASIC-1, HW0: data cable contact problem while doing first ODI test with the oscilloscope. Second measurement with multimeter and oscilloscope today was OK with good signal quality. 5 2026-03-09 12:15:13.030793 GSI
M3DR0B2000542A2 ASIC-1, HW6, ASIC-3, HW4: data cable contact problem while doing first ODI test with the oscilloscope. Second measurement with multimeter and oscilloscope today was OK with good signal quality. 5 2026-03-09 12:18:46.096725 GSI
M8UL4T3010223B2 ODI all ok 4 2026-03-09 12:47:40.988488 GSI
M8UL4B3010223A2 ODI all ok 4 2026-03-09 12:47:44.782192 GSI
M8UL4T2010222B2 ODI all ok 4 2026-03-09 12:48:11.962686 GSI
M8UL4B2010222A2 ODI all ok 4 2026-03-09 12:48:14.072781 GSI
M8UL4B1010221A2 ODI all ok 4 2026-03-09 12:49:03.942607 GSI
M8UL4T0010220B2 ODI all ok 4 2026-03-09 12:49:55.133542 GSI
M8UL4B0010220A2 ODI all ok 4 2026-03-09 12:50:18.014036 GSI
M8UL4B4010224A2 ODI all ok 4 2026-03-09 12:51:00.19345 GSI
M4DL4T3001173A2 ODI all ok 4 2026-03-10 10:45:36.498574 GSI
M4DL4T2101172A2 ODI all ok 4 2026-03-10 10:45:40.281802 GSI
M4DL4T1001171A2 ODI all ok 4 2026-03-10 10:45:42.354346 GSI
M4DL4T0001170A2 ODI all ok 4 2026-03-10 10:45:44.108962 GSI
M4DL4B0001170B2 ODI all ok 4 2026-03-10 10:45:46.271885 GSI
M4DL4B1001171B2 ODI all ok 4 2026-03-10 10:45:47.924922 GSI
M4DL4B2101172B2 ODI all ok 4 2026-03-10 10:45:49.573699 GSI
M4DL4B3001173B2 ODI all ok 4 2026-03-10 10:45:51.408504 GSI
M5UR2T1011161A2 ULX done, P ASIC 0_UL0, tested & Globtop 3 2026-03-11 08:07:30.346498 GSI
M7UL3T4010394B2 ULX done, FEB-B ASIC 6_UL0_P, FEB-test & Globtop 3 2026-03-11 08:10:28.041109 GSI
M7UR6B1011261B2 ULX done, FEB-B, ASIC 3_UL0_P, FEB-test & Globtop 3 2026-03-11 08:13:02.746917 GSI
M8UL2B3010223A2 ULX done, FEB-B, ASIC 1_UL0_N, FEB-test & Globtop 3 2026-03-11 08:17:43.326464 GSI
M8UL2B0010220A2 ULX done, FEB-B, ASIC 1_UL0_N. FEB-test & Globtop 3 2026-03-11 08:19:17.854126 GSI
M1DL3T2001102A2 ULX done, FEB-A, ASIC 2_UL0_P, FEB-test & Globtop 3 2026-03-11 08:20:52.207748 GSI
M7DR4T1000221B2 ULX done, FEB-B, ASIC 0_UL0_P, FEB-test & Globtop 3 2026-03-11 08:23:23.220063 GSI
M4UR3B0011310B2 ULX done, FEB-B, ASIC 0_UL0_P, FEB-test & Globtop 3 2026-03-11 08:24:43.001676 GSI
M3UL1B0010120A5 ODI checked with osziloscope by Ralf an all ODI ok. 4 2026-03-11 13:14:56.827102 GSI
M3UL1T0010120B5 ODI checked with osziloscope by Ralf an all ODI ok. 4 2026-03-11 13:15:44.958739 GSI
M1UR0B1011511B5 ODI Tested All Ok with Osc. 5 2026-03-11 15:29:58.098803 GSI
M6DL2T3001203A2 Fine scratches in the edge in P side, IV was OK before assembly 80 2026-03-12 08:46:45.052245 GSI
M8UR3T4011224A2 FEB A (ULX): -ASIC1 - UL1 to UL0 -ASIC3 - UL1 to UL0 FEB B (ULX, New chips): -ASIC1 - UL1 to UL0 -ASIC2 - New -ASIC7 - New 5 2026-03-12 10:42:48.22977 GSI
M8UL2T2010222B2 Replaced ASIC1_HW6 5 2026-03-12 13:22:36.266403 GSI
M0DR1T2000092B2 IV curve passed test. EoL current 12 uA. 76 2026-03-12 13:32:06.852011 GSI
M4DL0T3001613A2 ODI all ok 4 2026-03-12 13:37:14.022954 GSI
M4DL0T2001612A2 ODI all ok 4 2026-03-12 13:37:16.261583 GSI
M4DL0T1001611A2 ODI all ok 4 2026-03-12 13:37:18.206711 GSI
M4DL0T0001610A2 ODI all ok 4 2026-03-12 13:37:20.055602 GSI
M4DL0B0001610B2 ODI all ok 4 2026-03-12 13:37:23.166202 GSI
M4DL0B1101611B2 ODI all ok 4 2026-03-12 13:37:25.066818 GSI
M4DL0B2001612B2 ODI all ok 4 2026-03-12 13:37:27.004626 GSI
M4DL0B3101613B2 ODI all ok 4 2026-03-12 13:37:28.643368 GSI
M7DR6T3000243B2 IV curve passed 76 2026-03-12 13:38:25.886546 GSI
M0DR1B4000094A2 to be rebuilt 76 2026-03-12 13:42:24.436692 GSI
M0DL0T2001502A2 IV and long-term bias test passed 76 2026-03-12 13:47:09.929398 GSI
M6DR1B0000200A2 ODI all ok 4 2026-03-12 13:49:09.806871 GSI
M8UR5T2011232A2 ODI all ok 4 2026-03-12 13:50:43.114134 GSI
M5DR6B1000191A2 IV passed, long-term curve settled to 11 uA - passed 76 2026-03-12 13:52:23.034826 GSI
M8UR3T4011224A2 chipcables N-side 2 and 7 exchanged due to ODI problems, ULX ASIC 1_UL0, on P-side ULX, ASIC 1_UL0 and ASIC 3_UL_0 3 2026-03-12 14:23:54.49138 GSI
M1DL5T1001111A5 ODI issues, uplinks tested with multimeter & Oscilloscope, P-side: FEB-A: ASIC 2_UL4 and ASIC 4_UL1, N-side: ASIC 3_UL4P shows OL, all uplinks necessary? 3 2026-03-13 09:06:06.155886 GSI
M0DR3B2000102A5 uplinks tested with oscilloscope, ODI issue, P-side: FEB-A ASIC 3_UL4, all uplinks necessary? 3 2026-03-13 09:10:06.679218 GSI
M1DL5T1001111A5 ODI issue, all uplinks needed? 3 2026-03-13 09:13:09.958335 GSI
M0DR1B4100094A2 Module created 76 2026-03-13 10:56:38.830273 GSI
M3UL3B2010122A2 ODI all ok 4 2026-03-13 13:43:43.844257 GSI
M3UL3B4010124A2 ODI all ok 4 2026-03-13 13:43:50.206019 GSI
M1DL5T1001111A5 according to Joerg this module needs just 3 uplinks 3 2026-03-16 08:28:22.089589 GSI
M0DR3B2000102A5 according to Joerg just 3 uplinks are needed 3 2026-03-16 08:29:52.336182 GSI
M6DL0T4001584A2 ODI all ok 4 2026-03-16 10:51:21.684088 GSI
M6DL0T3001583A2 ODI all ok 4 2026-03-16 10:51:24.449211 GSI
M6DL0T2001582A2 ODI all ok 4 2026-03-16 10:51:26.6461 GSI
M6DL0T1001581A2 ODI all ok 4 2026-03-16 10:51:28.421796 GSI
M6DL0T0001580A2 ODI all ok 4 2026-03-16 10:51:30.949353 GSI
M6DL0B0001580B2 ODI all ok 4 2026-03-16 10:51:32.590083 GSI
M6DL0B1001581B2 ODI all ok 4 2026-03-16 10:51:35.120931 GSI
M6DL0B2001582B2 ODI all ok 4 2026-03-16 10:51:41.235122 GSI
M6DL0B3001583B2 ODI all ok 4 2026-03-16 10:51:42.931286 GSI
M6DL0B4101584B2 ODI all ok 4 2026-03-16 10:51:47.804598 GSI
M0DL0B2001502B2 ASIC 3, HW 4 on N-side - was replaced 5 2026-03-16 11:28:54.140053 GSI
M5UR0B2011562B2 FEB-A ASIC6 was replaced 5 2026-03-16 13:16:56.948787 GSI
M2DL0B1001531B2 was set to ODI-tested without clarifying whether to fix many broken channels. I hereby set it back to "pending" 81 2026-03-16 13:19:44.587868
M5UR0B3011563B2 On this module one chip is being replaced. It has been set to ODI-OK too early. Set back to pending 81 2026-03-16 13:31:16.145488
M0DR1T2000092B2 ODI Test still missing 81 2026-03-16 13:38:42.333567
M0DL0T2001502A2 ODI test still missing 81 2026-03-16 13:42:55.289903
M8UL6B0010240A2 ASIC6 was replaced 5 2026-03-16 13:55:50.568248 GSI
M4DR5T1000181B2 FEB "A" ASIC0, ASIC3 - New, ASIC4 - UL1 to UL0 (ULX); FEB "B" UL1 to UL0 (ULX) 5 2026-03-16 14:37:48.593149 GSI
M3DR2T4000124B2 We accepted previous slow breakdown behaviour which was cured with dryout procedure. Now ok on ladder. 76 2026-03-16 16:00:28.286477 GSI
M4UL0T0010550B2 At least one chip was replaced. Module goes back to QA in HL, waiting to be fully tested. CJS and JH. 76 2026-03-16 16:17:32.094221 GSI
M5DL1T3001163A2 n-side ASIC #2 was replaced. Now back to QA in HL. 76 2026-03-16 16:29:32.70671 GSI
M6DR3B4000204A2 current OK. ODI OK. Ready for ladder. 76 2026-03-16 16:33:25.22588 GSI
M8UL2T3010223B2 ASICs have been replaced. Full test in HL needed. 76 2026-03-16 16:36:50.461821 GSI
M8UL2T2010222B2 ASIC was replaced. Full test in HL needed. 76 2026-03-16 16:38:09.793129 GSI
M8UL4T4010224B2 First module with ULX. To very full functioning, test in HL needed. Exemplary for future ULX cases. 76 2026-03-16 16:40:55.396401 GSI
M8UL6B0010240A2 To be checked in HL after ASIC exchange. Or was this done already? 76 2026-03-16 16:43:52.094259 GSI
M8UL6B2010242A2 Finding "ODI low": what does that mean? Passed or not? Candidate for ULX. 76 2026-03-16 16:46:42.56216 GSI
M6UR1T2011352A2 Check whether really ready for ladder. Was the ODI check with the replaced ASIC and cable? 76 2026-03-16 16:56:16.753472 GSI
M8UR3T4011224A2 Module fully repaired. Waiting for test in HL. 76 2026-03-16 17:06:31.574871 GSI
M5UL5T2010182B2 ODI all ok 4 2026-03-17 11:19:11.149099 GSI
M5UL5T1010181B2 ODI all ok 4 2026-03-17 11:19:14.151623 GSI
M5UL5T0010180B2 ODI all ok 4 2026-03-17 11:19:15.84675 GSI
M5UL5B0010180A2 ODI all ok 4 2026-03-17 11:19:17.625671 GSI
M5UL5B1010181A2 ODI all ok 4 2026-03-17 11:19:19.300911 GSI
M5UL5B2010182A2 ODI all ok 4 2026-03-17 11:19:20.878071 GSI
M1UL1T0010090B5 Correction: ODI not tested and this module is in HL Issue : Input pulse generator is not injecting pulse for ASIC 1 (HW_0) Recommended to replace ASIC 77 2026-03-17 12:49:56.005301 GSI
M8UL6B2010242A2 During ODI uplink 0 (one line-> 1.6kohms) -> HW_ID 1. But for this module one uplink is required. Hence passed. 77 2026-03-17 13:04:10.468666 GSI
M6UR1T2011352A2 Clearified with Anju's statement: Yes, the module is retested on 15.12.2025 which is after repair. Then tested for ODI. So, yes this module is ready for ladder assembly. 76 2026-03-17 14:27:36.76709 GSI
M6UR1T2011352A2 and ODI OK 76 2026-03-17 14:29:42.924274 GSI
M1UL1B1010091A5 tested with oscilloscope, FEB-A ASIC 2(HW 5) _UL2 bad 3 2026-03-17 14:59:18.612978 GSI
M1UL1T1010091B5 tested with oscilloscope, all UL ok 3 2026-03-17 15:01:44.62261 GSI
M1UL1B0010090A5 tested with oscilloscope, all UL ok 3 2026-03-17 15:03:52.041728 GSI
M1DL5T0001110A5 tested with oscilloscope, all UL ok 3 2026-03-17 15:05:37.276538 GSI
M1DL5B0001110B5 tested with oscilloscope, all UL ok 3 2026-03-17 15:06:48.861387 GSI
M8UR1T2011222A2 Asymmetric current (difference is 5microA). 77 2026-03-18 00:11:59.676158 GSI
M0DL0T2001502A2 ODI test still missing, agreed with Kerstin to set to tested in HH 81 2026-03-18 10:59:46.881657
M0DR1T2000092B2 ODI test still missing 81 2026-03-18 11:04:26.173814
M5UR4T2011172A2 During the assemble on the ladder, after several attempts to fix the sensor in the tool it was not posible to do it with less than 20 micrometers gap. 80 2026-03-18 11:16:24.373643 GSI
M8UR3T2011222A2 spare cables ordered March 16 81 2026-03-18 11:16:38.71361
M8UL0B3010603A2 cable set delivered March 16 81 2026-03-18 11:19:43.242225
M8UL0B2010602A2 Spare cable L60-M02 NS delivered 16. March 81 2026-03-18 11:22:44.046208
M4DR5T1000181B2 rework ongoing, one chip cable still missing 81 2026-03-18 11:27:19.272642
M8UL2B2010222A2 chip cables ordered 81 2026-03-18 11:29:52.270715
M8UL2B1010221A2 spare cables ordered 16.03.26 81 2026-03-18 11:33:17.396807
M8UR1B3011223B2 complete cable set ordered 16.03.26 81 2026-03-18 11:35:03.528032
M2DL0T2001532A2 Adrian to check module tests 81 2026-03-18 11:44:28.899062
M8UL6B2010242A2 ULX to be done on HW-ID 1 p or n side to be done! 81 2026-03-18 11:55:09.739431
M5DL1B0101160B2 ODI all ok 4 2026-03-18 14:33:51.202206 GSI
M2DL0T2001532A2 Module is fully accepted (checked with Adrian), may be placed onto ladder 81 2026-03-18 17:29:21.482513
M1UL1T0010090B5 Agreed with Adrian that all channels are active even though one chip has defective pulsers. Now only ODI remains to be tested 81 2026-03-19 11:02:38.401532
M6DL4T4001204A2 ODI all ok 4 2026-03-19 12:49:12.557766 GSI
M6DL4T3001203A2 ODI all ok 4 2026-03-19 12:49:15.485014 GSI
M6DL4T2001202A2 ODI all ok 4 2026-03-19 12:49:17.3462 GSI
M6DL4T1001201A2 ODI all ok 4 2026-03-19 12:49:19.232085 GSI
M6DL4T0001200A2 ODI all ok 4 2026-03-19 12:49:20.956433 GSI
M6DL4B0001200B2 ODI all ok 4 2026-03-19 12:49:22.801763 GSI
M6DL4B1001201B2 ODI all ok 4 2026-03-19 12:49:24.69495 GSI
M6DL4B2001202B2 ODI all ok 4 2026-03-19 12:49:26.301023 GSI
M6DL4B3001203B2 ODI all ok 4 2026-03-19 12:49:28.098158 GSI
M6DL4B4001204B2 ODI all ok 4 2026-03-19 12:49:29.454554 GSI
M1UL1T0010090B5 ODI tested in HL. IT is FEB8_5 module, still to test hidden ODI in GSI. 77 2026-03-19 14:55:54.52481 GSI
M8UL4T4010224B2 Jörg tested in detail the very first ULX solution on this module. Everything is fine so now the module is ready for integration onto a ladder 81 2026-03-19 16:58:24.286333
M8UL4T4010224B2 module is allocated in red cabinet in STS-lab E10 Detlab 81 2026-03-19 16:59:13.215713
M1DL5B1001111B5 total 60 broken channels (28 on n-side and 32 on p-side). spread randomly 77 2026-03-20 11:11:00.291643 GSI
M5UL1T4010164B2 ODI all ok 4 2026-03-20 12:48:04.760251 GSI
M5UL1T3010163B2 ODI all ok 4 2026-03-20 12:48:25.639319 GSI
M5UL1T2010162B2 ODI all ok 4 2026-03-20 12:48:29.545027 GSI
M5UL1T0010160B2 ODI all ok 4 2026-03-20 12:48:32.271251 GSI
M5UL1B0010160A2 ODI all ok 4 2026-03-20 12:48:34.386474 GSI
M5UL1B1010161A2 ODI all ok 4 2026-03-20 12:48:36.141955 GSI
M5UL1B2010162A2 ODI all ok 4 2026-03-20 12:48:38.292234 GSI
M5UL1B4010164A2 ODI all ok 4 2026-03-20 12:48:39.730962 GSI
M5UL1B3010163A2 ODI failed: FEB B (N-Side) (HW2) ASIC3_UL0_P = 634,4 Ohm, (HW4) ASIC5_UL0_P = 612,9 Ohm 4 2026-03-20 12:52:04.225142 GSI
M5UL1T1010161B2 ODI failed: FEB A (N-Side) (HW1) ASIC6_UL0_P = 651 Ohm, 4 2026-03-20 12:53:15.346846 GSI
M1DR4T1000101B2 Very tiny asymmetric current (0.5 microA) 77 2026-03-20 17:48:44.619793 GSI
M8UL2T3010223B2 Slightly high noise for z-strips 77 2026-03-20 17:53:36.420564 GSI
M1DL5B1001111B5 All ODI okay 77 2026-03-20 17:55:15.350755 GSI
M0DL2T0001090A5 ODI Problem. The module was tested using an oscilloscope. It was found that ASIC0 HW7 had a low amplitude of 474 mV. The corresponding capacitor was accessed, and the measured resistance was 1.3 kΩ. 5 2026-03-23 10:05:59.748225 GSI
M5DL5T2001182A2 ODI all ok 4 2026-03-23 14:47:39.892852 GSI
M5DL5T1001181A2 ODI all ok 4 2026-03-23 14:47:43.107634 GSI
M5DL5T0001180A2 ODI all ok 4 2026-03-23 14:47:45.113683 GSI
M5DL5B0001180B2 ODI all ok 4 2026-03-23 14:47:46.691884 GSI
M5DL5B1001181B2 ODI all ok 4 2026-03-23 14:47:48.296237 GSI
M5DL5B2001182B2 ODI all ok 4 2026-03-23 14:47:50.079241 GSI
M5UL1T1010161B2 81 2026-03-23 16:36:11.850198
M5UL1B3010163A2 81 2026-03-23 16:37:47.61826
M0DL2T0001090A5 Jörg Lehnert identified that here with only 4 out of 5 uplinks, there will be no headrrom at all over the nominally needed bandwidth left. Oleksandr will check, whether it is feasible to replace the chip. 81 2026-03-23 16:59:02.364103
M2DL0T0001530A2 ODI all OK 80 2026-03-24 09:12:53.149377 GSI
M8UR1B2011222B2 ODI all OK 80 2026-03-24 09:14:14.57722 GSI
M8UR1B4011224B2 ULX FEB "B" ASIC4 UL1 to UL0, ASIC6 UL1 to UL0 5 2026-03-24 13:17:07.558446 GSI
M8UL6B2010242A2 ULX FEB "B" ASIC0 UL1 to UL0 5 2026-03-24 13:18:50.375941 GSI
M6UR1B4011354B2 The module is still good. Despite the observations: The current during IV testing raises up to ~ 18 uA at 150 V, exhibiting a plateau. Then a unstable current establishes, lowing from 18 uA to 10 uA in rapid spiking. This was seen previously during module testing, but at higher current (32 uA) and the rapid spiking to lower valies starting only at 200 V. 76 2026-03-24 13:59:16.564807 GSI
M8UL6B0010240A2 ULX FEB "B" ASIC1 UL1 to UL0, FEB "A" ASIC1 UL1 to UL0, ASIC7 UL1 to UL0 5 2026-03-24 14:27:21.563998 GSI
M0DL2T0001090A5 Oleksandr checks feasibility to replace one chip 81 2026-03-24 16:31:24.209368
M5UL1B3010163A2 agreed to set these all as finished 81 2026-03-25 09:33:30.019345
M5UL1T1010161B2 agreed to set this module as finished on ladder 81 2026-03-25 09:34:57.25902
M8UR3T2011222A2 ASICs 0,1 - were replaced 22.01.2026 5 2026-03-25 10:15:12.435513 GSI
M7DR6B2000242A2 Module Passed the Functional testing in HL 82 2026-03-25 12:00:07.387281
M5DL3T3001173A2 ODI all ok 4 2026-03-25 13:42:52.374117 GSI
M5DL3T2001172A2 ODI all ok 4 2026-03-25 13:43:20.308883 GSI
M5DL3T1001171A2 ODI all ok 4 2026-03-25 13:43:22.579314 GSI
M5DL3T0001170A2 ODI all ok 4 2026-03-25 13:43:24.352592 GSI
M5DL3B0001170B2 ODI all ok 4 2026-03-25 13:43:25.950303 GSI
M5DL3B1001171B2 ODI all ok 4 2026-03-25 13:43:27.5789 GSI
M5DL3B3001173B2 ODI all ok 4 2026-03-25 13:43:30.801349 GSI
M0DL2T0001090A5 Oleksandr will change chip, microcables are available 81 2026-03-25 14:37:25.264142
M5UL3T3010173B2 ODI all ok 4 2026-03-25 14:42:19.975193 GSI
M5UL3T2010172B2 ODI all ok 4 2026-03-25 14:42:22.179268 GSI
M5UL3T1010171B2 ODI all ok 4 2026-03-25 14:42:25.207598 GSI
M5UL3T0110170B2 ODI all ok 4 2026-03-25 14:42:28.322126 GSI
M5UL3B0010170A2 ODI all ok 4 2026-03-25 14:42:30.577378 GSI
M5UL3B1010171A2 ODI all ok 4 2026-03-25 14:42:32.165465 GSI
M5UL3B2010172A2 ODI all ok 4 2026-03-25 14:42:33.930542 GSI
M5UL3B3010173A2 ODI all ok 4 2026-03-25 14:42:35.741554 GSI
M3UL3T0010120B2 Sensor broken while assembly 4 2026-03-26 09:21:56.129875 GSI
M3UL3B0010120A2 Sensor broken while assembly 4 2026-03-26 09:25:34.594094 GSI
M8UL2T2010222B2 ODI is okay 83 2026-03-26 11:41:33.551523
M0DL0B2001502B2 ODI is okay 83 2026-03-26 11:42:10.162487
M2UR5B0011300B5 ODI is okay 83 2026-03-26 11:42:59.349292
M0DL2T0001090A5 ASIC0 HW7 was replaced 5 2026-03-26 17:00:42.543337 GSI
M5UR0B3011563B2 ASIC1 was replaced 5 2026-03-26 17:02:22.851458 GSI
M2DR1T3000123B2 ODI is okay 83 2026-03-26 17:04:59.006046
M2DR1B3000123A2 ODI is okay 83 2026-03-26 17:05:36.067223
M2DR1B4000124A2 ODI is okay 83 2026-03-26 17:05:49.715325
M2UR5T1011301A5 ODI is okay 83 2026-03-27 10:14:41.97743
M3UR4T2011132A2 ODI is okay 83 2026-03-27 10:15:49.186114
M3UR4B3011133B2 ODI is okay 83 2026-03-27 10:16:19.872972
M2DR1T4000124B2 ODI is okay 83 2026-03-27 10:17:12.770993
M2UR5T0011300A5 ODI is okay 83 2026-03-27 10:30:59.815799
M5UR0B3011563B2 The ASIC1 was re-bonded to the sensor and tested 5 2026-03-30 10:50:32.642033 GSI
M0DL2T0001090A5 The ASIC0 was re-bonded to the sensor and tested 5 2026-03-30 10:59:20.809979 GSI
M0DR1T2000092B2 ODI all ok 4 2026-03-30 13:03:42.287349 GSI
M0DL0T2001502A2 ODI all ok 4 2026-03-30 13:13:53.936137 GSI
M3UL3T0110120B2 Module created 76 2026-03-30 13:16:32.537832 GSI
M3UL3B0110120A2 Module created 76 2026-03-30 13:17:21.511248 GSI
M6UL6T1010381B2 ODI all ok 4 2026-03-31 13:38:37.619223 GSI
M6UL6T0010380B2 ODI all ok 4 2026-03-31 13:38:39.626228 GSI
M6UL6B0110380A2 ODI all ok 4 2026-03-31 13:38:41.446207 GSI
M6UL6B1010381A2 ODI all ok 4 2026-03-31 13:38:43.112804 GSI
M7UL5T2010402B2 ODI all ok 4 2026-03-31 13:38:50.041093 GSI
M7UL5T1010401B2 ODI all ok 4 2026-03-31 13:38:52.143115 GSI
M7UL5T0010400B2 ODI all ok 4 2026-03-31 13:38:54.229178 GSI
M7UL5B0010400A2 ODI all ok 4 2026-03-31 13:38:55.936399 GSI
M7UL5B1010401A2 ODI all ok 4 2026-03-31 13:38:57.533861 GSI
M7UL5B2010402A2 ODI all ok 4 2026-03-31 13:38:59.163573 GSI
M2UR1T4011284A2 ULX FEB "A" ASIC4 UL1 to UL0 5 2026-04-01 14:35:11.992677 GSI
M4UL0T0010550B2 1. Replacement of ASIC_HW_4 on the P-side is successful. 2. N-side ASIC_HW_4 AFE remains operational despite not responding to the internal pulse generator. Status: Passed with Errors. 83 2026-04-01 14:50:24.390667
M4UL0T0010550B2 ODI issues found before retesting in MT (17.03.2026) ASIC2_ HW 3 on P-side (UL0 and UL 1, 1.6 kΩ before/after MT) 83 2026-04-01 14:50:47.223155
M1UL1T0010090B5 ASIC DOES count noise hits like other healthy ASICs, Analog front-end WORKS, PASSED w/ ISSUES, ASIC has no valid calibration file (to use default TRIM settings) 83 2026-04-01 14:54:29.782286
M7UR0B4011594B2 Replacement of ASIC_HW_2 on P-side was successful. N-side FEB: 3186A2 1.8V domain shows elevated current consumption. 1. N-side ASIC HW_0 Low VDDM (Very Low Amplification) 2. P-side ASIC HW_0 remains operational despite no proper response to internally generated pulses. 83 2026-04-01 14:57:07.588556
M7UR0B4011594B2 ODI is okay 83 2026-04-01 14:57:21.52138
M3UR4B0011130B2 N-side: ASIC 0_UL0_P, and ASIC 0_UL0_N have globtop And ASIC 1_UL1_N shows 50 Ω ASIC 7_UL0_P, ASIC 7_UL0_N, ASIC 7_UL1_P, ASIC 7_UL1_N have glob top P-side : ASIC_HW 0, Uplink is missing during the functional test, but ODI is okay for this ASIC HW 0 Module needs 1 uplink. ENC looks good. 83 2026-04-01 15:03:47.076014