14:04:45:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:04:45:ST3_Shared:INFO:	                         FEB-Sensor                         
14:04:45:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:05:25:ST3_ModuleSelector:INFO:	M8UL2T2010222B2
14:05:25:ST3_ModuleSelector:INFO:	18054
14:05:25:febtest:INFO:	Testing FEB with SN 1217
14:05:27:smx_tester:INFO:	Scanning setup
14:05:27:elinks:INFO:	Disabling clock on downlink 0
14:05:27:elinks:INFO:	Disabling clock on downlink 1
14:05:27:elinks:INFO:	Disabling clock on downlink 2
14:05:27:elinks:INFO:	Disabling clock on downlink 3
14:05:27:elinks:INFO:	Disabling clock on downlink 4
14:05:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:05:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:05:27:elinks:INFO:	Disabling clock on downlink 0
14:05:27:elinks:INFO:	Disabling clock on downlink 1
14:05:27:elinks:INFO:	Disabling clock on downlink 2
14:05:27:elinks:INFO:	Disabling clock on downlink 3
14:05:27:elinks:INFO:	Disabling clock on downlink 4
14:05:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:05:27:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:05:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:05:27:elinks:INFO:	Disabling clock on downlink 0
14:05:27:elinks:INFO:	Disabling clock on downlink 1
14:05:27:elinks:INFO:	Disabling clock on downlink 2
14:05:27:elinks:INFO:	Disabling clock on downlink 3
14:05:27:elinks:INFO:	Disabling clock on downlink 4
14:05:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:05:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:05:27:elinks:INFO:	Disabling clock on downlink 0
14:05:27:elinks:INFO:	Disabling clock on downlink 1
14:05:27:elinks:INFO:	Disabling clock on downlink 2
14:05:27:elinks:INFO:	Disabling clock on downlink 3
14:05:27:elinks:INFO:	Disabling clock on downlink 4
14:05:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:05:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:05:27:elinks:INFO:	Disabling clock on downlink 0
14:05:27:elinks:INFO:	Disabling clock on downlink 1
14:05:27:elinks:INFO:	Disabling clock on downlink 2
14:05:27:elinks:INFO:	Disabling clock on downlink 3
14:05:27:elinks:INFO:	Disabling clock on downlink 4
14:05:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:05:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:05:27:setup_element:INFO:	Scanning clock phase
14:05:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:27:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:28:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:05:28:setup_element:INFO:	Eye window for uplink 0 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:05:28:setup_element:INFO:	Eye window for uplink 1 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:05:28:setup_element:INFO:	Eye window for uplink 2 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:05:28:setup_element:INFO:	Eye window for uplink 3 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:05:28:setup_element:INFO:	Eye window for uplink 4 : _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:05:28:setup_element:INFO:	Eye window for uplink 5 : _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:05:28:setup_element:INFO:	Eye window for uplink 6 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
14:05:28:setup_element:INFO:	Eye window for uplink 7 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
14:05:28:setup_element:INFO:	Eye window for uplink 8 : __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:28:setup_element:INFO:	Eye window for uplink 9 : __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:28:setup_element:INFO:	Eye window for uplink 10: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:05:28:setup_element:INFO:	Eye window for uplink 11: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:05:28:setup_element:INFO:	Eye window for uplink 12: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:05:28:setup_element:INFO:	Eye window for uplink 13: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:05:28:setup_element:INFO:	Eye window for uplink 14: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:05:28:setup_element:INFO:	Eye window for uplink 15: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:05:28:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 1
14:05:28:setup_element:INFO:	Scanning data phases
14:05:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:33:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:05:33:setup_element:INFO:	Eye window for uplink 0 : ______XXXXXX____________________________
Data delay found: 28
14:05:33:setup_element:INFO:	Eye window for uplink 1 : __XXXXX_________________________________
Data delay found: 24
14:05:33:setup_element:INFO:	Eye window for uplink 2 : ______XXXXXX____________________________
Data delay found: 28
14:05:33:setup_element:INFO:	Eye window for uplink 3 : ___XXXXXXX______________________________
Data delay found: 26
14:05:33:setup_element:INFO:	Eye window for uplink 4 : __XXXXX_________________________________
Data delay found: 24
14:05:33:setup_element:INFO:	Eye window for uplink 5 : XXX__________________________________XXX
Data delay found: 19
14:05:33:setup_element:INFO:	Eye window for uplink 6 : X___________________________________XXXX
Data delay found: 18
14:05:33:setup_element:INFO:	Eye window for uplink 7 : ________________________________XXXXX___
Data delay found: 14
14:05:33:setup_element:INFO:	Eye window for uplink 8 : ___________________XXXX_________________
Data delay found: 0
14:05:33:setup_element:INFO:	Eye window for uplink 9 : _______________________XXXXX____________
Data delay found: 5
14:05:33:setup_element:INFO:	Eye window for uplink 10: _______________________XXXXX____________
Data delay found: 5
14:05:33:setup_element:INFO:	Eye window for uplink 11: ___________________________XXXX_________
Data delay found: 8
14:05:33:setup_element:INFO:	Eye window for uplink 12: ________________________XXXXX___________
Data delay found: 6
14:05:33:setup_element:INFO:	Eye window for uplink 13: ___________________________XXXXX________
Data delay found: 9
14:05:33:setup_element:INFO:	Eye window for uplink 14: _______________________XXXXXX___________
Data delay found: 5
14:05:33:setup_element:INFO:	Eye window for uplink 15: _________________________XXXXXX_________
Data delay found: 7
14:05:33:setup_element:INFO:	Setting the data phase to 28 for uplink 0
14:05:33:setup_element:INFO:	Setting the data phase to 24 for uplink 1
14:05:33:setup_element:INFO:	Setting the data phase to 28 for uplink 2
14:05:33:setup_element:INFO:	Setting the data phase to 26 for uplink 3
14:05:33:setup_element:INFO:	Setting the data phase to 24 for uplink 4
14:05:33:setup_element:INFO:	Setting the data phase to 19 for uplink 5
14:05:33:setup_element:INFO:	Setting the data phase to 18 for uplink 6
14:05:33:setup_element:INFO:	Setting the data phase to 14 for uplink 7
14:05:33:setup_element:INFO:	Setting the data phase to 0 for uplink 8
14:05:33:setup_element:INFO:	Setting the data phase to 5 for uplink 9
14:05:33:setup_element:INFO:	Setting the data phase to 5 for uplink 10
14:05:33:setup_element:INFO:	Setting the data phase to 8 for uplink 11
14:05:33:setup_element:INFO:	Setting the data phase to 6 for uplink 12
14:05:33:setup_element:INFO:	Setting the data phase to 9 for uplink 13
14:05:34:setup_element:INFO:	Setting the data phase to 5 for uplink 14
14:05:34:setup_element:INFO:	Setting the data phase to 7 for uplink 15
14:05:34:setup_element:INFO:	Beginning SMX ASICs map scan
14:05:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:34:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:34:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:05:34:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:05:34:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:05:34:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:05:34:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:05:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:05:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:05:34:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:05:34:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:05:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:05:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:05:34:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:05:34:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:05:34:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:05:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:05:35:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:05:35:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:05:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:05:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:05:36:setup_element:INFO:	Performing Elink synchronization
14:05:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:36:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:05:36:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:05:36:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:05:36:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x0
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x1
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x2
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x3
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x4
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x5
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x6
14:05:37:ST3_emu_feb:DEBUG:	Chip address:  	0x7
14:05:37:febtest:INFO:	Init all SMX (CSA): 30
14:05:51:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:05:52:febtest:INFO:	01-00 | XA-000-08-002-003-007-010-07 |  66.4 | 1076.3
14:05:52:febtest:INFO:	08-01 | XA-000-08-002-003-007-013-07 |  63.2 | 1076.3
14:05:52:febtest:INFO:	03-02 | XA-000-08-002-003-007-006-07 |  63.2 | 1094.2
14:05:52:febtest:INFO:	10-03 | XA-000-08-002-003-007-019-00 |  72.8 | 1040.3
14:05:52:febtest:INFO:	05-04 | XA-000-08-002-003-007-005-07 |  53.6 | 1130.0
14:05:53:febtest:INFO:	12-05 | XA-000-08-002-003-007-016-00 |  66.4 | 1076.3
14:05:53:febtest:INFO:	07-06 | XA-000-08-002-003-007-017-00 |  56.8 | 1118.1
14:05:53:febtest:INFO:	14-07 | XA-000-08-002-003-007-011-07 |  47.3 | 1130.0
14:05:54:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:05:56:ST3_smx:INFO:	chip: 1-0 	 69.560482 C 	 1082.281915 mV
14:05:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:05:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:05:56:ST3_smx:INFO:		Electrons
14:05:56:ST3_smx:INFO:	# loops 0
14:05:58:ST3_smx:INFO:	# loops 1
14:05:59:ST3_smx:INFO:	# loops 2
14:06:01:ST3_smx:INFO:	# loops 3
14:06:03:ST3_smx:INFO:	# loops 4
14:06:04:ST3_smx:INFO:	Total # of broken channels: 0
14:06:04:ST3_smx:INFO:	List of broken channels: []
14:06:04:ST3_smx:INFO:	Total # of broken channels: 1
14:06:04:ST3_smx:INFO:	List of broken channels: [127]
14:06:06:ST3_smx:INFO:	chip: 8-1 	 66.365920 C 	 1082.281915 mV
14:06:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:06:ST3_smx:INFO:		Electrons
14:06:06:ST3_smx:INFO:	# loops 0
14:06:08:ST3_smx:INFO:	# loops 1
14:06:09:ST3_smx:INFO:	# loops 2
14:06:11:ST3_smx:INFO:	# loops 3
14:06:13:ST3_smx:INFO:	# loops 4
14:06:14:ST3_smx:INFO:	Total # of broken channels: 0
14:06:14:ST3_smx:INFO:	List of broken channels: []
14:06:14:ST3_smx:INFO:	Total # of broken channels: 2
14:06:14:ST3_smx:INFO:	List of broken channels: [61, 109]
14:06:16:ST3_smx:INFO:	chip: 3-2 	 66.365920 C 	 1100.211760 mV
14:06:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:16:ST3_smx:INFO:		Electrons
14:06:16:ST3_smx:INFO:	# loops 0
14:06:18:ST3_smx:INFO:	# loops 1
14:06:19:ST3_smx:INFO:	# loops 2
14:06:21:ST3_smx:INFO:	# loops 3
14:06:23:ST3_smx:INFO:	# loops 4
14:06:24:ST3_smx:INFO:	Total # of broken channels: 0
14:06:24:ST3_smx:INFO:	List of broken channels: []
14:06:24:ST3_smx:INFO:	Total # of broken channels: 2
14:06:24:ST3_smx:INFO:	List of broken channels: [97, 101]
14:06:26:ST3_smx:INFO:	chip: 10-3 	 75.957063 C 	 1052.299440 mV
14:06:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:26:ST3_smx:INFO:		Electrons
14:06:26:ST3_smx:INFO:	# loops 0
14:06:28:ST3_smx:INFO:	# loops 1
14:06:29:ST3_smx:INFO:	# loops 2
14:06:31:ST3_smx:INFO:	# loops 3
14:06:32:ST3_smx:INFO:	# loops 4
14:06:34:ST3_smx:INFO:	Total # of broken channels: 0
14:06:34:ST3_smx:INFO:	List of broken channels: []
14:06:34:ST3_smx:INFO:	Total # of broken channels: 9
14:06:34:ST3_smx:INFO:	List of broken channels: [0, 11, 19, 21, 23, 33, 37, 57, 118]
14:06:36:ST3_smx:INFO:	chip: 5-4 	 56.797143 C 	 1141.874115 mV
14:06:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:36:ST3_smx:INFO:		Electrons
14:06:36:ST3_smx:INFO:	# loops 0
14:06:37:ST3_smx:INFO:	# loops 1
14:06:39:ST3_smx:INFO:	# loops 2
14:06:41:ST3_smx:INFO:	# loops 3
14:06:42:ST3_smx:INFO:	# loops 4
14:06:44:ST3_smx:INFO:	Total # of broken channels: 0
14:06:44:ST3_smx:INFO:	List of broken channels: []
14:06:44:ST3_smx:INFO:	Total # of broken channels: 1
14:06:44:ST3_smx:INFO:	List of broken channels: [19]
14:06:45:ST3_smx:INFO:	chip: 12-5 	 66.365920 C 	 1088.263500 mV
14:06:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:45:ST3_smx:INFO:		Electrons
14:06:45:ST3_smx:INFO:	# loops 0
14:06:47:ST3_smx:INFO:	# loops 1
14:06:49:ST3_smx:INFO:	# loops 2
14:06:50:ST3_smx:INFO:	# loops 3
14:06:52:ST3_smx:INFO:	# loops 4
14:06:53:ST3_smx:INFO:	Total # of broken channels: 0
14:06:53:ST3_smx:INFO:	List of broken channels: []
14:06:53:ST3_smx:INFO:	Total # of broken channels: 0
14:06:53:ST3_smx:INFO:	List of broken channels: []
14:06:55:ST3_smx:INFO:	chip: 7-6 	 56.797143 C 	 1124.048640 mV
14:06:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:06:55:ST3_smx:INFO:		Electrons
14:06:55:ST3_smx:INFO:	# loops 0
14:06:57:ST3_smx:INFO:	# loops 1
14:06:58:ST3_smx:INFO:	# loops 2
14:07:00:ST3_smx:INFO:	# loops 3
14:07:02:ST3_smx:INFO:	# loops 4
14:07:03:ST3_smx:INFO:	Total # of broken channels: 0
14:07:03:ST3_smx:INFO:	List of broken channels: []
14:07:03:ST3_smx:INFO:	Total # of broken channels: 1
14:07:03:ST3_smx:INFO:	List of broken channels: [45]
14:07:05:ST3_smx:INFO:	chip: 14-7 	 50.430383 C 	 1141.874115 mV
14:07:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:07:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:07:05:ST3_smx:INFO:		Electrons
14:07:05:ST3_smx:INFO:	# loops 0
14:07:07:ST3_smx:INFO:	# loops 1
14:07:08:ST3_smx:INFO:	# loops 2
14:07:10:ST3_smx:INFO:	# loops 3
14:07:11:ST3_smx:INFO:	# loops 4
14:07:13:ST3_smx:INFO:	Total # of broken channels: 0
14:07:13:ST3_smx:INFO:	List of broken channels: []
14:07:13:ST3_smx:INFO:	Total # of broken channels: 6
14:07:13:ST3_smx:INFO:	List of broken channels: [51, 53, 57, 61, 63, 73]
14:07:13:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:07:13:febtest:INFO:	01-00 | XA-000-08-002-003-007-010-07 |  69.6 | 1106.2
14:07:14:febtest:INFO:	08-01 | XA-000-08-002-003-007-013-07 |  66.4 | 1100.2
14:07:14:febtest:INFO:	03-02 | XA-000-08-002-003-007-006-07 |  66.4 | 1118.1
14:07:14:febtest:INFO:	10-03 | XA-000-08-002-003-007-019-00 |  76.0 | 1070.3
14:07:14:febtest:INFO:	05-04 | XA-000-08-002-003-007-005-07 |  56.8 | 1159.7
14:07:15:febtest:INFO:	12-05 | XA-000-08-002-003-007-016-00 |  69.6 | 1106.2
14:07:15:febtest:INFO:	07-06 | XA-000-08-002-003-007-017-00 |  60.0 | 1141.9
14:07:15:febtest:INFO:	14-07 | XA-000-08-002-003-007-011-07 |  50.4 | 1159.7
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_08_19-14_04_45
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1217| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_NAME: 18054 | SIZE: 62x124 | GRADE: A
MODULE_NAME: M8UL2T2010222B2
LADDER_NAME: L8UL201022
------------------------------------------------------------
VI_before_Init : ['2.449', '1.5920', '1.848', '2.3390', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.1190', '1.850', '2.5500', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.0270', '1.850', '0.5358', '0.000', '0.0000', '0.000', '0.0000']