07:37:53:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:37:53:ST3_Shared:INFO:	                         FEB-Sensor                         
07:37:53:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:38:27:ST3_ModuleSelector:INFO:	M8UL2T0010220B2
07:38:27:ST3_ModuleSelector:INFO:	10322
07:38:27:febtest:INFO:	Testing FEB with SN 1219
07:38:29:smx_tester:INFO:	Scanning setup
07:38:29:elinks:INFO:	Disabling clock on downlink 0
07:38:29:elinks:INFO:	Disabling clock on downlink 1
07:38:29:elinks:INFO:	Disabling clock on downlink 2
07:38:29:elinks:INFO:	Disabling clock on downlink 3
07:38:29:elinks:INFO:	Disabling clock on downlink 4
07:38:29:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:38:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:38:29:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:38:29:elinks:INFO:	Disabling clock on downlink 0
07:38:29:elinks:INFO:	Disabling clock on downlink 1
07:38:29:elinks:INFO:	Disabling clock on downlink 2
07:38:29:elinks:INFO:	Disabling clock on downlink 3
07:38:29:elinks:INFO:	Disabling clock on downlink 4
07:38:29:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:38:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
07:38:29:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
07:38:29:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:38:29:elinks:INFO:	Disabling clock on downlink 0
07:38:29:elinks:INFO:	Disabling clock on downlink 1
07:38:29:elinks:INFO:	Disabling clock on downlink 2
07:38:29:elinks:INFO:	Disabling clock on downlink 3
07:38:29:elinks:INFO:	Disabling clock on downlink 4
07:38:29:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:38:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:38:29:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:38:29:elinks:INFO:	Disabling clock on downlink 0
07:38:29:elinks:INFO:	Disabling clock on downlink 1
07:38:29:elinks:INFO:	Disabling clock on downlink 2
07:38:29:elinks:INFO:	Disabling clock on downlink 3
07:38:29:elinks:INFO:	Disabling clock on downlink 4
07:38:29:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:38:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
07:38:30:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:38:30:elinks:INFO:	Disabling clock on downlink 0
07:38:30:elinks:INFO:	Disabling clock on downlink 1
07:38:30:elinks:INFO:	Disabling clock on downlink 2
07:38:30:elinks:INFO:	Disabling clock on downlink 3
07:38:30:elinks:INFO:	Disabling clock on downlink 4
07:38:30:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:38:30:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
07:38:30:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:38:30:setup_element:INFO:	Scanning clock phase
07:38:30:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:38:30:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:38:30:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
07:38:30:setup_element:INFO:	Eye window for uplink 0 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
07:38:30:setup_element:INFO:	Eye window for uplink 1 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
07:38:30:setup_element:INFO:	Eye window for uplink 2 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
07:38:30:setup_element:INFO:	Eye window for uplink 3 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
07:38:30:setup_element:INFO:	Eye window for uplink 4 : ___________________________________________________________________XXXXXXX______
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 5 : ___________________________________________________________________XXXXXXX______
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 6 : ___________________________________________________________________XXXXXXX______
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 7 : ___________________________________________________________________XXXXXXX______
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 8 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 9 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
07:38:30:setup_element:INFO:	Eye window for uplink 10: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
07:38:30:setup_element:INFO:	Eye window for uplink 11: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
07:38:30:setup_element:INFO:	Eye window for uplink 12: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
07:38:30:setup_element:INFO:	Eye window for uplink 13: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
07:38:30:setup_element:INFO:	Eye window for uplink 14: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
07:38:30:setup_element:INFO:	Eye window for uplink 15: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
07:38:30:setup_element:INFO:	Setting the clock phase to 30 for group 0, downlink 1
07:38:30:setup_element:INFO:	Scanning data phases
07:38:30:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:38:30:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:38:36:setup_element:INFO:	Data phase scan results for group 0, downlink 1
07:38:36:setup_element:INFO:	Eye window for uplink 0 : ________XXXXX___________________________
Data delay found: 30
07:38:36:setup_element:INFO:	Eye window for uplink 1 : ___XXXXX________________________________
Data delay found: 25
07:38:36:setup_element:INFO:	Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
07:38:36:setup_element:INFO:	Eye window for uplink 3 : __XXXXX_________________________________
Data delay found: 24
07:38:36:setup_element:INFO:	Eye window for uplink 4 : XXXXX__________________________________X
Data delay found: 21
07:38:36:setup_element:INFO:	Eye window for uplink 5 : X__________________________________XXXXX
Data delay found: 17
07:38:36:setup_element:INFO:	Eye window for uplink 6 : __________________________________XXXX__
Data delay found: 15
07:38:36:setup_element:INFO:	Eye window for uplink 7 : _____________________________XXXXXX_____
Data delay found: 11
07:38:36:setup_element:INFO:	Eye window for uplink 8 : ______________________XXXX______________
Data delay found: 3
07:38:36:setup_element:INFO:	Eye window for uplink 9 : ___________________________XXXXX________
Data delay found: 9
07:38:36:setup_element:INFO:	Eye window for uplink 10: ______________________XXXXXX____________
Data delay found: 4
07:38:36:setup_element:INFO:	Eye window for uplink 11: __________________________XXXXX_________
Data delay found: 8
07:38:36:setup_element:INFO:	Eye window for uplink 12: ___________________________XXXXX________
Data delay found: 9
07:38:36:setup_element:INFO:	Eye window for uplink 13: ______________________________XXXXXX____
Data delay found: 12
07:38:36:setup_element:INFO:	Eye window for uplink 14: ________________________XXXXX___________
Data delay found: 6
07:38:36:setup_element:INFO:	Eye window for uplink 15: __________________________XXXXX_________
Data delay found: 8
07:38:36:setup_element:INFO:	Setting the data phase to 30 for uplink 0
07:38:36:setup_element:INFO:	Setting the data phase to 25 for uplink 1
07:38:36:setup_element:INFO:	Setting the data phase to 27 for uplink 2
07:38:36:setup_element:INFO:	Setting the data phase to 24 for uplink 3
07:38:36:setup_element:INFO:	Setting the data phase to 21 for uplink 4
07:38:36:setup_element:INFO:	Setting the data phase to 17 for uplink 5
07:38:36:setup_element:INFO:	Setting the data phase to 15 for uplink 6
07:38:36:setup_element:INFO:	Setting the data phase to 11 for uplink 7
07:38:36:setup_element:INFO:	Setting the data phase to 3 for uplink 8
07:38:36:setup_element:INFO:	Setting the data phase to 9 for uplink 9
07:38:36:setup_element:INFO:	Setting the data phase to 4 for uplink 10
07:38:36:setup_element:INFO:	Setting the data phase to 8 for uplink 11
07:38:36:setup_element:INFO:	Setting the data phase to 9 for uplink 12
07:38:36:setup_element:INFO:	Setting the data phase to 12 for uplink 13
07:38:36:setup_element:INFO:	Setting the data phase to 6 for uplink 14
07:38:36:setup_element:INFO:	Setting the data phase to 8 for uplink 15
07:38:36:setup_element:INFO:	Beginning SMX ASICs map scan
07:38:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:38:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:38:36:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
07:38:36:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
07:38:36:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
07:38:36:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
07:38:36:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
07:38:36:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
07:38:36:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
07:38:36:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
07:38:36:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
07:38:36:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
07:38:37:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
07:38:37:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
07:38:37:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
07:38:37:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
07:38:37:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
07:38:37:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
07:38:37:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
07:38:37:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
07:38:37:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
07:38:39:setup_element:INFO:	Performing Elink synchronization
07:38:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:38:39:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:38:39:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
07:38:39:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
07:38:39:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
07:38:39:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x0
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x1
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x2
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x3
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x4
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x5
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x6
07:38:39:ST3_emu_feb:DEBUG:	Chip address:  	0x7
07:38:39:febtest:INFO:	Init all SMX (CSA): 30
07:38:54:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:38:54:febtest:INFO:	01-00 | XA-000-08-002-003-007-001-07 |  40.9 | 1135.9
07:38:54:febtest:INFO:	08-01 | XA-000-08-002-003-006-234-11 |  34.6 | 1147.8
07:38:55:febtest:INFO:	03-02 | XA-000-08-002-003-006-219-02 |  53.6 | 1094.2
07:38:55:febtest:INFO:	10-03 | XA-000-08-002-003-006-232-11 |  40.9 | 1124.0
07:38:55:febtest:INFO:	05-04 | XA-000-08-002-003-006-238-11 |  56.8 | 1088.3
07:38:55:febtest:INFO:	12-05 | XA-000-08-002-003-006-242-12 |  34.6 | 1147.8
07:38:55:febtest:INFO:	07-06 | XA-000-08-002-003-006-240-12 |  37.7 | 1159.7
07:38:56:febtest:INFO:	14-07 | XA-000-08-002-003-006-241-12 |  40.9 | 1130.0
07:38:57:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
07:38:59:ST3_smx:INFO:	chip: 1-0 	 40.898880 C 	 1141.874115 mV
07:38:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:38:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:38:59:ST3_smx:INFO:		Electrons
07:38:59:ST3_smx:INFO:	# loops 0
07:39:00:ST3_smx:INFO:	# loops 1
07:39:02:ST3_smx:INFO:	# loops 2
07:39:04:ST3_smx:INFO:	# loops 3
07:39:05:ST3_smx:INFO:	# loops 4
07:39:07:ST3_smx:INFO:	Total # of broken channels: 0
07:39:07:ST3_smx:INFO:	List of broken channels: []
07:39:07:ST3_smx:INFO:	Total # of broken channels: 1
07:39:07:ST3_smx:INFO:	List of broken channels: [127]
07:39:09:ST3_smx:INFO:	chip: 8-1 	 34.556970 C 	 1159.654860 mV
07:39:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:09:ST3_smx:INFO:		Electrons
07:39:09:ST3_smx:INFO:	# loops 0
07:39:11:ST3_smx:INFO:	# loops 1
07:39:12:ST3_smx:INFO:	# loops 2
07:39:14:ST3_smx:INFO:	# loops 3
07:39:16:ST3_smx:INFO:	# loops 4
07:39:17:ST3_smx:INFO:	Total # of broken channels: 0
07:39:17:ST3_smx:INFO:	List of broken channels: []
07:39:17:ST3_smx:INFO:	Total # of broken channels: 1
07:39:17:ST3_smx:INFO:	List of broken channels: [23]
07:39:19:ST3_smx:INFO:	chip: 3-2 	 53.612520 C 	 1106.178435 mV
07:39:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:19:ST3_smx:INFO:		Electrons
07:39:19:ST3_smx:INFO:	# loops 0
07:39:21:ST3_smx:INFO:	# loops 1
07:39:22:ST3_smx:INFO:	# loops 2
07:39:24:ST3_smx:INFO:	# loops 3
07:39:26:ST3_smx:INFO:	# loops 4
07:39:27:ST3_smx:INFO:	Total # of broken channels: 0
07:39:27:ST3_smx:INFO:	List of broken channels: []
07:39:27:ST3_smx:INFO:	Total # of broken channels: 1
07:39:27:ST3_smx:INFO:	List of broken channels: [84]
07:39:29:ST3_smx:INFO:	chip: 10-3 	 40.898880 C 	 1135.937260 mV
07:39:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:29:ST3_smx:INFO:		Electrons
07:39:29:ST3_smx:INFO:	# loops 0
07:39:31:ST3_smx:INFO:	# loops 1
07:39:32:ST3_smx:INFO:	# loops 2
07:39:34:ST3_smx:INFO:	# loops 3
07:39:36:ST3_smx:INFO:	# loops 4
07:39:37:ST3_smx:INFO:	Total # of broken channels: 0
07:39:37:ST3_smx:INFO:	List of broken channels: []
07:39:37:ST3_smx:INFO:	Total # of broken channels: 2
07:39:37:ST3_smx:INFO:	List of broken channels: [0, 127]
07:39:39:ST3_smx:INFO:	chip: 5-4 	 56.797143 C 	 1100.211760 mV
07:39:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:39:ST3_smx:INFO:		Electrons
07:39:39:ST3_smx:INFO:	# loops 0
07:39:41:ST3_smx:INFO:	# loops 1
07:39:42:ST3_smx:INFO:	# loops 2
07:39:44:ST3_smx:INFO:	# loops 3
07:39:46:ST3_smx:INFO:	# loops 4
07:39:47:ST3_smx:INFO:	Total # of broken channels: 0
07:39:47:ST3_smx:INFO:	List of broken channels: []
07:39:47:ST3_smx:INFO:	Total # of broken channels: 0
07:39:47:ST3_smx:INFO:	List of broken channels: []
07:39:49:ST3_smx:INFO:	chip: 12-5 	 34.556970 C 	 1159.654860 mV
07:39:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:49:ST3_smx:INFO:		Electrons
07:39:49:ST3_smx:INFO:	# loops 0
07:39:51:ST3_smx:INFO:	# loops 1
07:39:52:ST3_smx:INFO:	# loops 2
07:39:54:ST3_smx:INFO:	# loops 3
07:39:56:ST3_smx:INFO:	# loops 4
07:39:57:ST3_smx:INFO:	Total # of broken channels: 0
07:39:57:ST3_smx:INFO:	List of broken channels: []
07:39:57:ST3_smx:INFO:	Total # of broken channels: 0
07:39:57:ST3_smx:INFO:	List of broken channels: []
07:39:59:ST3_smx:INFO:	chip: 7-6 	 37.726682 C 	 1171.483840 mV
07:39:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:39:59:ST3_smx:INFO:		Electrons
07:39:59:ST3_smx:INFO:	# loops 0
07:40:01:ST3_smx:INFO:	# loops 1
07:40:02:ST3_smx:INFO:	# loops 2
07:40:04:ST3_smx:INFO:	# loops 3
07:40:06:ST3_smx:INFO:	# loops 4
07:40:07:ST3_smx:INFO:	Total # of broken channels: 15
07:40:07:ST3_smx:INFO:	List of broken channels: [92, 94, 98, 100, 102, 104, 106, 110, 112, 114, 116, 120, 122, 124, 126]
07:40:07:ST3_smx:INFO:	Total # of broken channels: 36
07:40:07:ST3_smx:INFO:	List of broken channels: [52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 110, 112, 114, 116, 120, 122, 124, 126]
07:40:09:ST3_smx:INFO:	chip: 14-7 	 40.898880 C 	 1135.937260 mV
07:40:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:40:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
07:40:09:ST3_smx:INFO:		Electrons
07:40:09:ST3_smx:INFO:	# loops 0
07:40:11:ST3_smx:INFO:	# loops 1
07:40:12:ST3_smx:INFO:	# loops 2
07:40:14:ST3_smx:INFO:	# loops 3
07:40:15:ST3_smx:INFO:	# loops 4
07:40:17:ST3_smx:INFO:	Total # of broken channels: 0
07:40:17:ST3_smx:INFO:	List of broken channels: []
07:40:17:ST3_smx:INFO:	Total # of broken channels: 2
07:40:17:ST3_smx:INFO:	List of broken channels: [0, 1]
07:40:17:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:40:18:febtest:INFO:	01-00 | XA-000-08-002-003-007-001-07 |  40.9 | 1165.6
07:40:18:febtest:INFO:	08-01 | XA-000-08-002-003-006-234-11 |  34.6 | 1183.3
07:40:18:febtest:INFO:	03-02 | XA-000-08-002-003-006-219-02 |  53.6 | 1124.0
07:40:18:febtest:INFO:	10-03 | XA-000-08-002-003-006-232-11 |  44.1 | 1153.7
07:40:18:febtest:INFO:	05-04 | XA-000-08-002-003-006-238-11 |  60.0 | 1118.1
07:40:19:febtest:INFO:	12-05 | XA-000-08-002-003-006-242-12 |  34.6 | 1183.3
07:40:19:febtest:INFO:	07-06 | XA-000-08-002-003-006-240-12 |  40.9 | 1183.3
07:40:19:febtest:INFO:	14-07 | XA-000-08-002-003-006-241-12 |  44.1 | 1153.7
############################################################
#                   S U M M A R Y                          #
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{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

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#                   S U M M A R Y                          #
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TEST_NAME : FEB-Sensor
TEST_DATE : 24_08_16-07_37_53
OPERATOR  : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1219| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_NAME: 10322 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M8UL2T0010220B2
LADDER_NAME: L8UL201022
------------------------------------------------------------
VI_before_Init : ['2.449', '1.4520', '1.849', '2.0150', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9720', '1.850', '2.4310', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9820', '1.850', '0.5191', '0.000', '0.0000', '0.000', '0.0000']
07:42:24:ST3_Shared:INFO:	Listo of operators:Olga B.;