DDL633

class description - source file - inheritance tree

class DDL633 : public DModule


    public:

               DDL633 DDL633()
               DDL633 DDL633(Char_t* mdesc, UInt_t addr)
               DDL633 DDL633(DDL633&)
         virtual void ~DDL633()
                 void AndLogic(Int_t i)
              TClass* Class()
                 void Disable(Int_t i)
                 void Enable(Int_t i)
      virtual TClass* IsA() const
                Int_t IsAnd(Int_t i)
                Int_t IsDisabled(Int_t i)
                Int_t IsEnabled(Int_t i)
                Int_t IsOr(Int_t i)
                 void OrLogic(Int_t i)
         virtual void ReadVME()
         virtual void ResetModule()
         virtual void ShowMembers(TMemberInspector& insp, char* parent)
         virtual void Streamer(TBuffer& b)

  Data Members
    private:

      UShort_t fLogic  Logic

Class Description

 DL600 is a VME module built at Physics Institute of Heidelberg University.
 It houses 4 submodules, and I decided to treat these submodules in my
 software as separate VME modules. The submodules are:

 DL631 - input register
 DL632 - output register
 DL633 - AND/OR logic unit
 DL634 - fan-out

DDL633(Char_t *mdesc, UInt_t addr) : DModule("AND/OR Logic","DL633",mdesc,addr)

~DDL633()

void ReadVME()

void ResetModule()

Inline Functions

             DDL633 DDL633(Char_t* mdesc, UInt_t addr)
               void Enable(Int_t i)
               void Disable(Int_t i)
               void OrLogic(Int_t i)
               void AndLogic(Int_t i)
              Int_t IsEnabled(Int_t i)
              Int_t IsDisabled(Int_t i)
              Int_t IsAnd(Int_t i)
              Int_t IsOr(Int_t i)
            TClass* Class()
            TClass* IsA() const
               void ShowMembers(TMemberInspector& insp, char* parent)
               void Streamer(TBuffer& b)
             DDL633 DDL633(DDL633&)

Author: Dariusz Miskowiec
Last update: 1999

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