Vc  1.0.0-dev
SIMD Vector Classes for C++
cpuid.h
1 /* This file is part of the Vc library. {{{
2 Copyright © 2009-2015 Matthias Kretz <kretz@kde.org>
3 All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7  * Redistributions of source code must retain the above copyright
8  notice, this list of conditions and the following disclaimer.
9  * Redistributions in binary form must reproduce the above copyright
10  notice, this list of conditions and the following disclaimer in the
11  documentation and/or other materials provided with the distribution.
12  * Neither the names of contributing organizations nor the
13  names of its contributors may be used to endorse or promote products
14  derived from this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
17 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
20 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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23 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 
27 }}}*/
28 
29 #ifndef VC_CPUID_H_
30 #define VC_CPUID_H_
31 
32 #include "common/macros.h"
33 namespace Vc_VERSIONED_NAMESPACE
34 {
35 
51 class CpuId
52 {
53  typedef unsigned char uchar;
54  typedef unsigned short ushort;
55  typedef unsigned int uint;
56 
57  public:
58  enum ProcessorType {
59  OriginalOemProcessor = 0,
60  IntelOverDriveProcessor = 1,
61  DualProcessor = 2,
62  IntelReserved = 3
63  };
64 
71  static void init();
72 
74  static inline ushort cacheLineSize() { return static_cast<ushort>(s_cacheLineSize) * 8u; }
76  static inline ProcessorType processorType() { return s_processorType; }
78  static inline uint processorFamily() { return s_processorFamily; }
80  static inline uint processorModel() { return s_processorModel; }
82  static inline uint logicalProcessors() { return s_logicalProcessors; }
84  static inline bool isAmd () { return s_ecx0 == 0x444D4163; }
86  static inline bool isIntel () { return s_ecx0 == 0x6C65746E; }
88  static inline bool hasSse3 () { return s_processorFeaturesC & (1 << 0); }
90  static inline bool hasPclmulqdq() { return (s_processorFeaturesC & (1 << 1)) != 0; }
92  static inline bool hasMonitor() { return (s_processorFeaturesC & (1 << 3)) != 0; }
94  static inline bool hasVmx () { return (s_processorFeaturesC & (1 << 5)) != 0; }
96  static inline bool hasSmx () { return (s_processorFeaturesC & (1 << 6)) != 0; }
98  static inline bool hasEist () { return (s_processorFeaturesC & (1 << 7)) != 0; }
100  static inline bool hasTm2 () { return (s_processorFeaturesC & (1 << 8)) != 0; }
102  static inline bool hasSsse3() { return (s_processorFeaturesC & (1 << 9)) != 0; }
104  static inline bool hasFma () { return (s_processorFeaturesC & (1 << 12)) != 0; }
106  static inline bool hasCmpXchg16b() { return (s_processorFeaturesC & (1 << 13)) != 0; }
108  static inline bool hasPdcm () { return (s_processorFeaturesC & (1 << 15)) != 0; }
110  static inline bool hasDca() { return (s_processorFeaturesC & (1 << 18)) != 0; }
112  static inline bool hasSse41() { return (s_processorFeaturesC & (1 << 19)) != 0; }
114  static inline bool hasSse42() { return (s_processorFeaturesC & (1 << 20)) != 0; }
116  static inline bool hasMovbe() { return (s_processorFeaturesC & (1 << 22)) != 0; }
118  static inline bool hasPopcnt(){ return (s_processorFeaturesC & (1 << 23)) != 0; }
119  //static inline bool hasTscDeadline() { return (s_processorFeaturesC & (1 << 24)) != 0; }
121  static inline bool hasAes () { return (s_processorFeaturesC & (1 << 25)) != 0; }
122  //static inline bool hasXsave() { return (s_processorFeaturesC & (1 << 26)) != 0; }
124  static inline bool hasOsxsave() { return (s_processorFeaturesC & (1 << 27)) != 0; }
126  static inline bool hasAvx () { return (s_processorFeaturesC & (1 << 28)) != 0; }
128  static inline bool hasBmi1 () { return (s_processorFeatures7B& (1 << 3)) != 0; }
130  static inline bool hasHle () { return (s_processorFeatures7B& (1 << 4)) != 0; }
132  static inline bool hasAvx2 () { return (s_processorFeatures7B& (1 << 5)) != 0; }
134  static inline bool hasBmi2 () { return (s_processorFeatures7B& (1 << 8)) != 0; }
136  static inline bool hasRtm () { return (s_processorFeatures7B& (1 << 11)) != 0; }
137 
139  static inline bool hasAvx512f () { return (s_processorFeatures7B & (1u << 16)) != 0; }
141  static inline bool hasAvx512dq () { return (s_processorFeatures7B & (1u << 17)) != 0; }
143  static inline bool hasAvx512ifma() { return (s_processorFeatures7B & (1u << 21)) != 0; }
145  static inline bool hasAvx512pf () { return (s_processorFeatures7B & (1u << 26)) != 0; }
147  static inline bool hasAvx512er () { return (s_processorFeatures7B & (1u << 27)) != 0; }
149  static inline bool hasAvx512cd () { return (s_processorFeatures7B & (1u << 28)) != 0; }
151  static inline bool hasAvx512bw () { return (s_processorFeatures7B & (1u << 30)) != 0; }
153  static inline bool hasAvx512vl () { return (s_processorFeatures7B & (1u << 31)) != 0; }
155  static inline bool hasAvx512vbmi() { return (s_processorFeatures7C & (1u << 1)) != 0; }
156 
158  static inline bool hasF16c () { return (s_processorFeaturesC & (1 << 29)) != 0; }
160  static inline bool hasRdrand(){ return (s_processorFeaturesC & (1 << 30)) != 0; }
162  static inline bool hasFpu () { return (s_processorFeaturesD & (1 << 0)) != 0; }
163  static inline bool hasVme () { return (s_processorFeaturesD & (1 << 1)) != 0; }
165  static inline bool hasDe () { return (s_processorFeaturesD & (1 << 2)) != 0; }
167  static inline bool hasPse () { return (s_processorFeaturesD & (1 << 3)) != 0; }
169  static inline bool hasTsc () { return (s_processorFeaturesD & (1 << 4)) != 0; }
171  static inline bool hasMsr () { return (s_processorFeaturesD & (1 << 5)) != 0; }
173  static inline bool hasPae () { return (s_processorFeaturesD & (1 << 6)) != 0; }
175  static inline bool hasCx8 () { return (s_processorFeaturesD & (1 << 8)) != 0; }
177  static inline bool hasMtrr () { return (s_processorFeaturesD & (1 << 12)) != 0; }
179  static inline bool hasCmov () { return (s_processorFeaturesD & (1 << 15)) != 0; }
181  static inline bool hasClfsh() { return (s_processorFeaturesD & (1 << 19)) != 0; }
183  static inline bool hasAcpi () { return (s_processorFeaturesD & (1 << 22)) != 0; }
185  static inline bool hasMmx () { return (s_processorFeaturesD & (1 << 23)) != 0; }
187  static inline bool hasSse () { return (s_processorFeaturesD & (1 << 25)) != 0; }
189  static inline bool hasSse2 () { return (s_processorFeaturesD & (1 << 26)) != 0; }
190  static inline bool hasHtt () { return (s_processorFeaturesD & (1 << 28)) != 0; }
192  static inline bool hasSse4a() { return (s_processorFeatures8C & (1 << 6)) != 0; }
194  static inline bool hasMisAlignSse() { return (s_processorFeatures8C & (1 << 7)) != 0; }
196  static inline bool hasAmdPrefetch() { return (s_processorFeatures8C & (1 << 8)) != 0; }
198  static inline bool hasXop () { return (s_processorFeatures8C & (1 << 11)) != 0; }
200  static inline bool hasFma4 () { return (s_processorFeatures8C & (1 << 16)) != 0; }
202  static inline bool hasRdtscp() { return (s_processorFeatures8D & (1 << 27)) != 0; }
203  static inline bool has3DNow() { return (s_processorFeatures8D & (1u << 31)) != 0; }
204  static inline bool has3DNowExt() { return (s_processorFeatures8D & (1 << 30)) != 0; }
206  static inline uint L1Instruction() { return s_L1Instruction; }
208  static inline uint L1Data() { return s_L1Data; }
210  static inline uint L2Data() { return s_L2Data; }
212  static inline uint L3Data() { return s_L3Data; }
213  static inline ushort L1InstructionLineSize() { return s_L1InstructionLineSize; }
214  static inline ushort L1DataLineSize() { return s_L1DataLineSize; }
215  static inline ushort L2DataLineSize() { return s_L2DataLineSize; }
216  static inline ushort L3DataLineSize() { return s_L3DataLineSize; }
217  static inline uint L1Associativity() { return s_L1Associativity; }
218  static inline uint L2Associativity() { return s_L2Associativity; }
219  static inline uint L3Associativity() { return s_L3Associativity; }
220  static inline ushort prefetch() { return s_prefetch; }
221 
222  private:
223  static void interpret(uchar byte, bool *checkLeaf4);
224 
225  static uint s_ecx0;
226  static uint s_logicalProcessors;
227  static uint s_processorFeaturesC;
228  static uint s_processorFeaturesD;
229  static uint s_processorFeatures7B;
230  static uint s_processorFeatures7C;
231  static uint s_processorFeatures8C;
232  static uint s_processorFeatures8D;
233  static uint s_L1Instruction;
234  static uint s_L1Data;
235  static uint s_L2Data;
236  static uint s_L3Data;
237  static ushort s_L1InstructionLineSize;
238  static ushort s_L1DataLineSize;
239  static ushort s_L2DataLineSize;
240  static ushort s_L3DataLineSize;
241  static uint s_L1Associativity;
242  static uint s_L2Associativity;
243  static uint s_L3Associativity;
244  static ushort s_prefetch;
245  static uchar s_brandIndex;
246  static uchar s_cacheLineSize;
247  static uchar s_processorModel;
248  static uchar s_processorFamily;
249  static ProcessorType s_processorType;
250  static bool s_noL2orL3;
251 };
252 
253 }
254 
255 #endif // VC_CPUID_H_
static bool hasRtm()
Return whether the CPU supports transactional synchronization extensions.
Definition: cpuid.h:136
static uint processorModel()
Return the model number of the processor (vendor dependent).
Definition: cpuid.h:80
unsigned char uchar
unsigned char shorthand
Definition: types.h:64
static bool hasSmx()
Return whether the CPU supports the Safer Mode Extensions.
Definition: cpuid.h:96
unsigned int uint
unsigned int shorthand
Definition: types.h:60
static bool isIntel()
Return whether the CPU vendor is Intel.
Definition: cpuid.h:86
static bool hasAvx512vl()
Return whether the CPU supports AVX512vl.
Definition: cpuid.h:153
static bool hasSse4a()
Return whether the CPU supports SSE4a.
Definition: cpuid.h:192
static bool hasF16c()
Return whether the CPU supports 16-bit floating-point conversion instructions.
Definition: cpuid.h:158
static bool hasPae()
Return whether the CPU supports the Physical Address Extension.
Definition: cpuid.h:173
static bool hasAvx512dq()
Return whether the CPU supports AVX512dq.
Definition: cpuid.h:141
static bool hasVmx()
Return whether the CPU supports the Virtual Machine Extensions.
Definition: cpuid.h:94
static uint L2Data()
Return the size of the L2 cache.
Definition: cpuid.h:210
static bool hasMtrr()
Return whether the CPU supports Memory Type Range Registers.
Definition: cpuid.h:177
static bool hasAvx512cd()
Return whether the CPU supports AVX512cd.
Definition: cpuid.h:149
static bool hasAvx512f()
Return whether the CPU supports AVX512f.
Definition: cpuid.h:139
static bool hasOsxsave()
Return whether the CPU and OS support the XSETBV/XGETBV instructions.
Definition: cpuid.h:124
static bool hasPclmulqdq()
Return whether the CPU supports the PCLMULQDQ instruction.
Definition: cpuid.h:90
static bool hasMonitor()
Return whether the CPU supports the MONITOR/MWAIT instructions.
Definition: cpuid.h:92
static bool isAmd()
Return whether the CPU vendor is AMD.
Definition: cpuid.h:84
static bool hasMisAlignSse()
Return whether the CPU supports misaligned SSE instructions.
Definition: cpuid.h:194
static bool hasBmi1()
Return whether the CPU supports BMI1.
Definition: cpuid.h:128
static bool hasSse3()
Return whether the CPU supports SSE3.
Definition: cpuid.h:88
static bool hasPdcm()
Return whether the CPU supports the Perfmon and Debug Capability.
Definition: cpuid.h:108
static uint logicalProcessors()
Return the number of logical processors.
Definition: cpuid.h:82
static bool hasSse()
Return whether the CPU supports SSE.
Definition: cpuid.h:187
static bool hasAcpi()
Return whether the CPU supports ACPI.
Definition: cpuid.h:183
static bool hasPse()
Return whether the CPU contains Page Size Extensions.
Definition: cpuid.h:167
static bool hasAvx()
Return whether the CPU supports AVX.
Definition: cpuid.h:126
static bool hasSse42()
Return whether the CPU supports SSE 4.2.
Definition: cpuid.h:114
static bool hasAmdPrefetch()
Return whether the CPU supports the AMD prefetchw instruction.
Definition: cpuid.h:196
static uint L3Data()
Return the size of the L3 cache.
Definition: cpuid.h:212
static bool hasAvx512ifma()
Return whether the CPU supports AVX512ifma.
Definition: cpuid.h:143
static bool hasRdrand()
Return whether the CPU supports the RDRAND instruction.
Definition: cpuid.h:160
static bool hasCmov()
Return whether the CPU supports CMOV instructions.
Definition: cpuid.h:179
static bool hasClfsh()
Return whether the CPU supports the CLFLUSH instruction.
Definition: cpuid.h:181
static bool hasAes()
Return whether the CPU supports the AESNI instructions.
Definition: cpuid.h:121
static bool hasRdtscp()
Return whether the CPU supports the RDTSCP instruction.
Definition: cpuid.h:202
static bool hasCmpXchg16b()
Return whether the CPU supports CMPXCHG16B.
Definition: cpuid.h:106
static bool hasFpu()
Return whether the CPU contains an x87 FPU.
Definition: cpuid.h:162
This class is available for x86 / AMD64 systems to read and interpret information about the CPU's cap...
Definition: cpuid.h:51
static bool hasMmx()
Return whether the CPU supports MMX.
Definition: cpuid.h:185
static bool hasSse2()
Return whether the CPU supports SSE2.
Definition: cpuid.h:189
static bool hasAvx512er()
Return whether the CPU supports AVX512er.
Definition: cpuid.h:147
static bool hasCx8()
Return whether the CPU supports the CMPXCHG8B instruction.
Definition: cpuid.h:175
static uint L1Instruction()
Return the size of the L1 instruction cache.
Definition: cpuid.h:206
static bool hasDca()
Return whether the CPU supports Direct Cache Access: prefetch data from a memory mapped device...
Definition: cpuid.h:110
static bool hasBmi2()
Return whether the CPU supports BMI2.
Definition: cpuid.h:134
static bool hasFma()
Return whether the CPU supports FMA extensions using YMM state.
Definition: cpuid.h:104
static bool hasTm2()
Return whether the CPU supports Thermal Monitor 2.
Definition: cpuid.h:100
static ProcessorType processorType()
Return the ProcessorType.
Definition: cpuid.h:76
static bool hasAvx512pf()
Return whether the CPU supports AVX512pf.
Definition: cpuid.h:145
static bool hasXop()
Return whether the CPU supports the XOP instructions.
Definition: cpuid.h:198
static bool hasDe()
Return whether the CPU contains Debugging Extensions.
Definition: cpuid.h:165
unsigned short ushort
unsigned short shorthand
Definition: types.h:62
static bool hasFma4()
Return whether the CPU supports the FMA4 instructions.
Definition: cpuid.h:200
static uint processorFamily()
Return the family number of the processor (vendor dependent).
Definition: cpuid.h:78
static bool hasTsc()
Return whether the CPU supports the RDTSC instruction.
Definition: cpuid.h:169
static bool hasSsse3()
Return whether the CPU supports SSSE3.
Definition: cpuid.h:102
static uint L1Data()
Return the size of the L1 data cache.
Definition: cpuid.h:208
static bool hasAvx512vbmi()
Return whether the CPU supports AVX512vbmi.
Definition: cpuid.h:155
static bool hasPopcnt()
Return whether the CPU supports the POPCNT instruction.
Definition: cpuid.h:118
static bool hasEist()
Return whether the CPU supports the Enhanced Intel SpeedStep technology.
Definition: cpuid.h:98
static ushort cacheLineSize()
Return the cache line size in bits.
Definition: cpuid.h:74
static bool hasSse41()
Return whether the CPU supports SSE 4.1.
Definition: cpuid.h:112
static bool hasMsr()
Return whether the CPU supports the Model Specific Registers instructions.
Definition: cpuid.h:171
static bool hasAvx2()
Return whether the CPU supports AVX2.
Definition: cpuid.h:132
static bool hasHle()
Return whether the CPU supports transactional synchronization extensions.
Definition: cpuid.h:130
static bool hasMovbe()
Return whether the CPU supports the MOVBE instruction.
Definition: cpuid.h:116
static bool hasAvx512bw()
Return whether the CPU supports AVX512bw.
Definition: cpuid.h:151